WM8972L Datasheet, PDF (33/49 Pages) Wolfson Microelectronics plc – MONO CODEC FOR PORTABLE AUDIO APPLICATIONS

Preliminary Technical Data
WM8972L
The clocking of the WM8972L is controlled using the CLKDIV2, USB, and SR control bits. Setting the
CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode.
Each value of SR[4:0] selects one combination of MCLK division ratios and hence one combination
of sample rates (see next page). Since all sample rates are generated by dividing MCLK, their
accuracy depends on the accuracy of MCLK. If MCLK changes, the sample rates change
proportionately.
Note that some sample rates (e.g. 44.1kHz in USB mode) are approximated, i.e. they differ from their
target value by a very small amount. This is not audible, as the maximum deviation is only 0.27%
(8.0214kHz instead of 8kHz in USB mode). By comparison, a half-tone step corresponds to a 5.9%
change in pitch.
MCLK
MCLK
ADC SAMPLE RATE
DAC SAMPLE RATE
CLKDIV2=0 CLKDIV2=1
(ADCLRC)
(DACLRC)
‘Normal’ Clock Mode (‘*’ indicates backward compatibility with WM8731)
12.288 MHz 24.576 MHz
11.2896MHz 22.5792MHz
18.432MHz 36.864MHz
16.9344MHz 33.8688MHz
8 kHz (MCLK/1536)
8 kHz (MCLK/1536)
12 kHz (MCLK/1024)
16 kHz (MCLK/768)
24 kHz (MCLK/512)
32 kHz (MCLK/384)
48 kHz (MCLK/256)
48 kHz (MCLK/256)
96 kHz (MCLK/128)
8.0182 kHz (MCLK/1408)
8.0182 kHz (MCLK/1408)
11.025 kHz (MCLK/1024)
22.05 kHz (MCLK/512)
44.1 kHz (MCLK/256)
44.1 kHz (MCLK/256)
88.2 kHz (MCLK/128)
8 kHz (MCLK/2304)
8 kHz (MCLK/2304)
12 kHz (MCLK/1536)
16kHz (MCLK/1152)
24kHz (MCLK/768)
32 kHz (MCLK/576)
48 kHz (MCLK/384)
48 kHz (MCLK/384)
96 kHz (MCLK/192)
8.0182 kHz (MCLK/2112)
8.0182 kHz (MCLK/2112)
11.025 kHz (MCLK/1536)
22.05 kHz (MCLK/768)
44.1 kHz (MCLK/384)
44.1 kHz (MCLK/384)
88.2 kHz (MCLK/192)
8 kHz (MCLK/1536)
48 kHz (MCLK/256)
12 kHz (MCLK/1024)
16 kHz (MCLK/768)
24 kHz (MCLK/512)
32 kHz (MCLK/384)
8 kHz (MCLK/1536)
48 kHz (MCLK/256)
96 kHz (MCLK/128)
8.0182 kHz (MCLK/1408)
44.1 kHz (MCLK/256)
11.025 kHz (MCLK/1024)
22.05 kHz (MCLK/512)
8.0182 kHz (MCLK/1408)
44.1 kHz (MCLK/256)
88.2 kHz (MCLK/128)
8 kHz (MCLK/2304)
48 kHz (MCLK/384)
12 kHz (MCLK/1536)
16 kHz (MCLK/1152)
24 kHz (MCLK/768)
32 kHz (MCLK/576)
48 kHz (MCLK/384)
8 kHz (MCLK/2304)
96 kHz (MCLK/192)
8.0182 kHz (MCLK/2112)
44.1 kHz (MCLK/384)
11.025 kHz (MCLK/1536)
22.05 kHz (MCLK/768)
8.0182 kHz (MCLK/2112)
44.1 kHz (MCLK/384)
88.2 kHz (MCLK/192)
USB Mode (‘*’ indicates backward compatibility with WM8731)
12.000MHz 24.000MHz
8 kHz (MCLK/1500)
8 kHz (MCLK/1500)
8.0214 kHz (MCLK/1496)
8.0214 kHz (MCLK/1496)
11.0259 kHz (MCLK/1088)
12 kHz (MCLK/1000)
16kHz (MCLK/750)
22.0588kHz (MCLK/544)
24kHz (MCLK/500)
32 kHz (MCLK/375)
44.118 kHz (MCLK/272)
44.118 kHz (MCLK/272)
48 kHz (MCLK/250)
48 kHz (MCLK/250)
88.235kHz (MCLK/136)
96 kHz (MCLK/125)
8 kHz (MCLK/1500)
48 kHz (MCLK/250)
8.0214kHz (MCLK/1496)
44.118 kHz (MCLK/272)
11.0259kHz (MCLK/1088)
12 kHz (MCLK/1000)
16kHz (MCLK/750)
22.0588kHz (MCLK/544)
24kHz (MCLK/500)
32 kHz (MCLK/375)
8.0214kHz (MCLK/1496)
44.118 kHz (MCLK/272)
8 kHz (MCLK/1500)
48 kHz (MCLK/250)
88.235kHz (MCLK/136)
96 kHz (MCLK/125)
Table 29 Master Clock and Sample Rates
USB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SR [4:0] FILTER BCLK
TYPE (MS=1)
00110 *
00100 *
01000
01010
11100
01100 *
00010 *
00000 *
01110 *
10110 *
10100 *
11000
11010
10010 *
10000 *
11110 *
00111 *
00101 *
01001
01011
11101
01101 *
00001 *
00011 *
01111 *
10111 *
10101 *
11001
11011
10011 *
10001 *
11111 *
1
MCLK/4
1
MCLK/4
1
MCLK/4
1
MCLK/4
1
MCLK/4
1
MCLK/4
1
MCLK/4
1
MCLK/4
3
MCLK/2
1
MCLK/4
1
MCLK/4
1
MCLK/4
1
MCLK/4
1
MCLK/4
1
MCLK/4
3
MCLK/2
1
MCLK/6
1
MCLK/6
1
MCLK/6
1
MCLK/6
1
MCLK/6
1
MCLK/6
1
MCLK/6
1
MCLK/6
3
MCLK/3
1
MCLK/6
1
MCLK/6
1
MCLK/6
1
MCLK/6
1
MCLK/6
1
MCLK/6
3
MCLK/3
00110 *
0
MCLK
00100 *
0
MCLK
10111 *
1
MCLK
10101 *
1
MCLK
11001
1
MCLK
01000
0
MCLK
01010
0
MCLK
11011
1
MCLK
11100
0
MCLK
01100 *
0
MCLK
10011 *
1
MCLK
10001 *
1
MCLK
00010 *
0
MCLK
00000 *
0
MCLK
11111 *
3
MCLK
01110 *
2
MCLK
w
PTD Rev 2.2 June 2004
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