WM8776_05 Datasheet, PDF (33/57 Pages) Wolfson Microelectronics plc – 24-bit, 192kHz Stereo CODEC with 5 Channel I/P Multiplexer

Production Data
REGISTER
BIT
ADDRESS
R14 (0Eh)
7:0
0001110
Attenuation
ADCL
8
R15 (0Fh)
7:0
0001111
Attenuation
ADCR
8
R21 (15h)
8
0010101
ADC Input Mux
R21 (15h)
7
0010101
ADC Input Mux
6
WM8776
In addition a zero cross detect circuit is provided for the output PGA volume under the control of bit 7
(ZCEN) in the each attenuation register. When ZCEN is set the attenuation values are only updated
when the input signal to the gain stage is close to the analogue ground level. This minimises audible
clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which will
generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of
12.288MHz). The timeout clock may be disabled by setting TOD.
Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to
write the same attenuation value to both left and right volume control registers, saving on software
writes. The ADC volume and mute also applies to the bypass signal path.
LABEL
DEFAULT
DESCRIPTION
LAG[7:0]
11001111
(0dB)
Attenuation data for Left channel ADC gain in 0.5dB steps. See
Table 15.
ZCLA
RAG[7:0]
0
11001111
(0dB)
Left channel ADC zero cross enable:
0: Zero cross disabled
1: Zero cross enabled
Attenuation data for right channel ADC gain in 0.5dB steps. See
Table 15.
ZCRA
0
Right channel ADC zero cross enable:
0: Zero cross disabled
1: Zero cross enabled
LRBOTH
0
Right channel input PGA controlled by left channel register
0 : Right channel uses RAG.
1 : Right channel uses LAG.
MUTELA
0
Mute for left channel ADC
0: Mute Off
1: Mute on
MUTERA
0
Mute for right channel ADC
0: Mute Off
1: Mute on
ADC HIGHPASS FILTER DISABLE
The ADC digital filters contain a digital high pass filter. This defaults to enabled and can be disabled
using software control bit ADCHPD.
REGISTER ADDRESS
R11 (0Bh)
0001011
ADC Control
BIT LABEL
8 ADCHPD
DEFAULT
0
DESCRIPTION
ADC High pass filter disable:
0: High pass filter enabled
1: High pass filter disabled
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PD Rev 4.0 April 2005
33