WM8594_07 Datasheet, PDF (33/78 Pages) Wolfson Microelectronics plc – 24-bit 192kHz 2Vrms Multi-Channel CODEC

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WM8594
REGISTER
ADDRESS
R13
ADC_CTRL1
0Dh
BIT LABEL DEFAULT
7
ADC_
0
LRSWAP
8
ADCR_
0
INV
9
ADCL_
0
INV
11:10 ADC_
00
DATA_
SEL[1:0]
Table 24 ADC Channel Swap Control
DESCRIPTION
ADC Left/Right Swap
0 = Normal
1 = Swap left channel data into right channel
and vice-versa
ADCL and ADCR Output Signal Inversion
0 = Output not inverted
1 = Output inverted
ADC Data Output Select
00 = left data from ADCL, right data from
ADCR
01 = left data from ADCL, right data from
ADCL
10 = left data from ADCR, right data from
ADCR
11 = left data from ADCR, right data from
ADCL
HIGH PASS FILTER
The WM8594 includes a high pass filter to remove DC offsets. The high pass filter response is
shown on page 73. It is possible to disable the high pass filter by writing to ADC_HPD.
REGISTER
ADDRESS
R13
ADC_CTRL1
0Dh
BIT LABEL DEFAULT
12 ADC_HPD
0
Table 25 High Pass Filter Disable Control
DESCRIPTION
ADC High Pass Filter Disable
0 = High pass filter enabled
1 = High pass filter disabled
CLOCK SWITCHING
The input clocks to the ADC (ADCMCLK, ADCBCLK, ADCLRCLK) can be switched between sources
if the ADC is used to supply data to multiple DSPs or application processors. Uncontrolled switching
of clocks is not recommended as this may result in clock glitches being applied to the ADC.
The WM8594 can be configured to ignore the clock inputs so that the clocks can be switched
externally. This means that the WM8594 is not affected by any glitches that arise as a result of
switching clocks. The ADC should be configured to ignore the input clocks for the duration of the
period taken to switch the clocks.
REGISTER
ADDRESS
R37
ADC_CLK
25h
BIT LABEL DEFAULT
0
ADC_
0
SAFE_SW
Table 26 ADC Clock Switching Control
DESCRIPTION
ADC Clock Input Safe Switching
0 = Ignore ADC Clock Inputs
1 = Use ADC Clock Inputs
ANALOGUE ROUTING CONTROL
The WM8594 has a number of analogue paths, allowing flexible routing of a number of analogue
input signals and DAC output signals at levels up to 2Vrms. The analogue paths include volume
control with zero cross, optional soft ramp and soft mute, and flexible routing of analogue inputs and
DAC outputs to analogue outputs.
w
PP Rev 1.0 January 2007
33