WM8951L_07 Datasheet, PDF (31/42 Pages) Wolfson Microelectronics plc – Stereo ADC with Microphone Input and Clock Generator

Production Data
WM8951
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
The WM8951L can be controlled using a 3-wire serial interface. SDIN is used for the program data,
SCLK is used to clock in the program data and CSB is use to latch in the program data. The 3-wire
interface protocol is shown in Figure 23.
CSB
SCLK
SDIN
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Figure 23 3-Wire Serial Interface
Notes:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
3. CSB is edge sensitive not level sensitive. The data is latched on the rising edge of CSB.
2-WIRE SERIAL CONTROL MODE
The WM8951L supports a 2-wire serial interface. The WM8951L has one of two slave addresses that
are selected by setting the state of pin 26, (CSB).
SDIN
R ADDR
R/W
ACK
DATA B15-8 ACK
DATA B7-0
ACK
SCLK
START
STOP
Figure 24 2-Wire Serial Interface
Notes:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
CSB STATE
ADDRESS
0
0011010
1
0011011
Table 19 2-Wire MPU Interface Address Selection
To control the WM8951L on the 2-wire bus the master control device must initiate a data transfer by
establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high.
This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond
to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB
first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of
two available addresses for this device (see table 24). If the correct address is received and the R/W
bit is ‘0’, indicating a write, then the WM8951L will respond by pulling SDIN low on the next clock
pulse (ACK). The WM8951L is a write only device and will only respond to the R/W bit indicating a
write. If the address is not recognised the device will return to the idle condition and wait for a new
start condition and valid address.
Once the WM8951L has acknowledged a correct address, the controller will send eight data bits (bits
B15-B8). WM8951L will then acknowledge the sent data by pulling SDIN low for one clock pulse.
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PD Rev 4.1 December 2007
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