WAN0143 Datasheet, PDF (3/6 Pages) Wolfson Microelectronics plc – ADA and MASK Timing on WM9712

INTERFACE TIMING
WAN_0143
MASK
Frames
(SYNC)
AUXADC Conversion
(MASK = 11)
AUXADC Conversion
(MASK = 10)
Conv
AUXADC Conversion
(MASK = 01)
Conv
Delay
t _DEL
t _DEL
Conv
Conv
Delay
Delay
t _DEL
t _DEL
Conv
Conv
Delay
Conv
Delay
Conv
Delay
Conv
Delay
Conv
Figure 1 MASK Delay Timings (tDEL = 2 frames)
PARAMETER
Frame Delay set by register 76h
SYMBOL
tDEL
MIN
0
TYP
MAX
288
UNIT
frames
MASK
BCLK
SYNC
t_SETUP
t _HOLD
t_SETUP
t _HOLD
Figure 2 MASK Delay Timings
PARAMETER
SYMBOL MIN
TYP
Setup time from MASK edge to SYNC ¹
tSETUP
162.8
Hold time of MASK level from SYNC
rising edge.
tHOLD
81.4
MAX
UNIT
ns
ns
Note:
1. There must be at least two BCLK's between the rising edge of MASK and the rising edge of SYNC. Therefore, once MASK is
high there must be at least two BCLK rising edges prior to the SYNC pulse.
w
Rev 1.0 March 2004
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