WM8976_11 Datasheet, PDF (29/114 Pages) Wolfson Microelectronics plc – Stereo CODEC with Speaker Driver

Production Data
WM8976
The polarity of the output signal can also be changed under software control using the ADCLPOL
register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR register bit. With
ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1
the oversample rate is 128x which gives best performance.
REGISTER
ADDRESS
R14
ADC Control
BIT
LABEL
0
ADCLPOL
3
ADCOSR
Table 13 ADC Control
DEFAULT
DESCRIPTION
0
ADC polarity adjust:
0=normal
1=inverted
0
ADC oversample rate select:
0=64x (lower power)
1=128x (best performance)
SELECTABLE HIGH PASS FILTER
A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two modes
controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of
3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off frequency selectable
via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown in Table 15.
REGISTER
ADDRESS
R14
ADC Control
BIT
LABEL
8
HPFEN
7
HPFAPP
6:4
HPFCUT
Table 14 ADC Enable Control
DEFAULT
DESCRIPTION
1
High Pass Filter Enable
0=disabled
1=enabled
0
Select audio mode or application mode
0=Audio mode (1^st order, fc = ~3.7Hz)
1=Application mode (2^nd order, fc =
HPFCUT)
000
Application mode cut-off frequency
See Table 15 for details.
HPFCUT
SR=101/100
SR=011/010
SR=001/000
[2:0]
8 11.025 12
fs (kHz)
16 22.05 24
32 44.1 48
000
82
113 122 82
113 122 82 113 122
001
102 141 153 102 141 153 102 141 153
010
131 180 196 131 180 196 131 180 196
011
163 225 245 163 225 245 163 225 245
100
204 281 306 204 281 306 204 281 306
101
261 360 392 261 360 392 261 360 392
110
327 450 490 327 450 490 327 450 490
111
408 563 612 408 563 612 408 563 612
Table 15 High Pass Filter Cut-off Frequencies (HPFAPP=1). Values in Hz.
Note that the High Pass filter values (when HPFAPP=1) are calculated with the assumption that the
SR register bits are set correctly for the actual sample rate as shown in Table 15.
w
PD, Rev 4.5, November 2011
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