WM8734_06 Datasheet, PDF (25/46 Pages) Wolfson Microelectronics plc – Stereo Audio CODEC

WM8734
Production Data
In all modes DACLRC and ADCLRC must always change on the falling edge of BCLK, refer to Figure
16, Figure 17, Figure 18, Figure 19 and Figure 20.
Operating the digital audio interface in DSP mode allows ease of use for supporting the various
sample rates and word lengths. The only requirement is that all data is transferred within the correct
number of BCLK cycles to suit the chosen word length.
In order for the digital audio interface to offer similar support in the three other modes (Left Justified,
I²S and Right Justified), the DACLRC, ADCLRC and BCLK frequencies, continuity and mark-space
ratios need more careful consideration.
In Slave mode, DACLRC and ADCLRC inputs are not required to have a 50:50 mark-space ratio.
BCLK input need not be continuous. It is however required that there are sufficient BCLK cycles for
each DACLRC/ADCLRC transition to clock the chosen data word length.
In Master mode, DACLRC and ADCLRC will be output with a 50:50 mark-space ratio with BCLK
output at 64fs.
The ADC and DAC digital audio interface modes are software configurable as indicated in Table 7.
Note that dynamically changing the software format may result in erroneous operation of the
interfaces and is therefore not recommended. The length of the digital audio data is programmable at
16/20/24 or 32 bits. Refer to the software control table below. The data is signed 2’s complement.
Both ADC and DAC are fixed at the same data length. The ADC and DAC digital filters process data
using 24 bits. If the ADC is programmed to output 16 or 20 bit data then it strips the LSBs from the
24 bit data. If the ADC is programmed to output 32 bits then it packs the LSBs with zeros. If the DAC
is programmed to receive 16 or 20 bit data, the WM8734 packs the LSBs with zeros. If the DAC is
programmed to receive 32 bit data, then it strips the LSBs.
The DAC outputs can be swapped under software control using LRP and LRSWAP as shown in
Table 7. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses the
order of that a Left sample goes to the right DAC output and a Right sample goes to the left DAC
output. LRP swaps the phasing so that a Right/Left sampled pair is expected and preserves the
correct channel phase difference.
To accommodate system timing requirements the interpretation of BCLK may be inverted, this is
controlled vias the software shown in Table 6. This is especially appropriate for DSP mode.
ADCDAT lines are always outputs. They power up and return from standby low.
DACDAT is always an input. It is expected to be set low by the audio interface controller when the
WM8734 is powered off or in standby.
ADCLRC, DACLRC and BCLK can be either outputs or inputs depending on whether the device is
configured as a master or slave. If the device is a master then the ADCLRC, DACLRC and BCLK
signals are outputs that default low. If the device is a slave then the ADCLRC, DACLRC and BCLK
are inputs.
w
PD Rev 4.1 November 2006
25