WM8951L Datasheet, PDF (24/42 Pages) Wolfson Microelectronics plc – STEREO ADC WITH MICROPHONE INPUT AND CLOCK GENERATOR

WM8951L
Production Data
The ADC digital audio interface modes are software configurable as indicated in Table 8. Note that
dynamically changing the software format may result in erroneous operation of the interfaces and is
therefore not recommended.
The length of the digital audio data is programmable at 16/20/24 or 32 bits, in I2S or left justified
modes only. Refer to the software control table below. The data is signed 2’s complement. The ADC
digital filters process data using 24 bits. If the ADC is programmed to output 16 or 20 bit data then it
strips the LSBs from the 24 bit data. If the ADC is programmed to output 32 bits then it packs the
LSBs with zeros.
To accommodate system timing requirements the interpretation of BCLK maybe inverted, this is
controlled vias the software shown in Table 9. This is especially appropriate for DSP mode.
ADCDAT lines are always outputs. They power up and return from standby low.
ADCLRC and BCLK can be either outputs or inputs depending on whether the device is configured
as a master or slave. If the device is a master then BCLK is an output that defaults low. If the device
is a slave then BCLK is an input. It is expected that these are set low by the audio interface controller
when the WM8951L is powered off or in standby.
REGISTER
ADDRESS
0000111
Digital Audio
Interface
Format
BIT
LABEL
1:0 FORMAT[1:0]
3:2 IWL[1:0]
6
MS
7
BCLKINV
Table 9 Digital Audio Interface Control
DEFAULT
DESCRIPTION
10
Audio Data Format Select
11 = DSP Mode, frame sync + 2
data packed words
10 = I²S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
10
Input Audio Data Bit Length Select
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
0
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
0
Bit Clock Invert
1 = Invert BCLK
0 = Don’t invert BCLK
Note: If right justified 32 bit mode is selected then the WM8951L defaults to 24 bits.
MASTER AND SLAVE MODE OPERATION
The WM8951L can be configured as either a master or slave mode device. As a master mode device
the WM8951L controls sequencing of the data and clocks on the digital audio interface. As a slave
device the WM8951L responds with data to the clocks it receives over the digital audio interface. The
mode is set with the MS bit of the control register as shown in Table 10.
REGISTER
ADDRESS
0000111
Digital Audio Interface
Format
BIT
6
LABEL DEFAULT
MS
0
Table 10 Programming Master/Slave Modes
DESCRIPTION
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
As a master mode device the WM8951L controls the sequencing of data transfer (ADCDAT) and
output of clocks (BCLK, ADCLRC) over the digital audio interface. It uses the timing generated from
either its on-board crystal or the MCLK input as the reference for the clock and data transitions. This
is illustrated in Figure 21. ADCDAT is always an output from the WM8951L independent of master or
slave mode.
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PD Rev 4.0 May 2005
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