WM9712L_11 Datasheet, PDF (23/78 Pages) Wolfson Microelectronics plc – AC’97 Audio and Touchpanel CODEC

Production Data
WM9712L
REGISTER
ADDRESS
62h
ALC / Noise
Gate Control
BIT
15:14
13:11
8
9:10
60h
15:12
ALC Control
11:8
7:4
3:0
Table 9 ALC Control
LABEL
DEFAULT DESCRIPTION
ALCSEL
00
(OFF)
MAXGAIN 111
(+30dB)
ALCZC
0
ZC
11
TIMEOUT
ALCL
1011
(-12dB)
HLD
0000
(0ms)
DCY
0011
(192ms)
ATK
0010
(24ms)
ALC function select
00 = ALC off (PGA gain set by register)
01 = Right channel only
10 = Left channel only
11 = Stereo (PGA registers unused)
Note: Ensure that RECVOLL and RECVOLR
settings (reg. 1Ch) are the same before
entering this mode
PGA gain limit for ALC
111 = +30dB
110 = +24dB
….(6dB steps)
001 = -6dB
000 = -12dB
ALC Zero Cross enable (overrides ZC bit in
register 1Ch)
0: PGA Gain changes immediately
1: PGA Gain changes when signal is zero or
after time-out
Programmable zero cross timeout
11 2¹⁷ x MCLK period
10 2¹⁶ x MCLK period
01 2¹⁵ x MCLK period
00 2¹⁴ x MCLK period
ALC target – sets signal level at ADC input
0000 = -28.5dB FS
0001 = -27.0dB FS
… (1.5dB steps)
1110 = -7.5dB FS
1111 = -6dB FS
ALC hold time before gain is increased.
0000 = 0ms
0001 = 2.67ms
0010 = 5.33ms
… (time doubles with every step)
1111 = 43.691s
ALC decay (gain ramp-up) time
0000 = 24ms
0001 = 48ms
0010 = 96ms
… (time doubles with every step)
1010 or higher = 24.58s
ALC attack (gain ramp-down) time
0000 = 6ms
0001 = 12ms
0010 = 24ms
… (time doubles with every step)
1010 or higher = 6.14s
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PD, Rev 4.6, November 2011
23