WM8785 Datasheet, PDF (22/31 Pages) Wolfson Microelectronics plc – 24-Bit, 192kHz Stereo ADC

WM8785
Pre-Production
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB latches in a complete control word consisting of the last 16 bits.
CSB
SCLK
SDIN
latch
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
control register address
control register data bits
Figure 26 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8785 supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address
of each register in the WM8785).
The WM8785 operates as a slave device only. The controller indicates the start of data transfer with
a high to low transition on SDIN while SCLK remains high. This indicates that a device address and
data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight
bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the
address of the WM8785 and the R/W bit is ‘0’, indicating a write, then the WM8785 responds by
pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’,
the WM8785 returns to the idle condition and wait for a new start condition and valid address.
Once the WM8785 has acknowledged a correct address, the controller sends the first byte of control
data (B15 to B8, i.e. the WM8785 register address plus the first bit of register data). The WM8785
then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then
sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the
WM8785 acknowledges again by pulling SDIN low.
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8785 returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
SDIN
SCLK
START
DEVICE ADDRESS RD / WR ACK
(7 BITS)
BIT
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
ACK
(LOW)
register address and
1st register data bit
remaining 8 bits of
register data
STOP
Figure 27 2-Wire Serial Control Interface
The WM8785 device address is 0011010.
TIME DIVISION MULTIPLEXED DATA OUT
The WM8785 can be used to time division multiplex several data channels at once. For example, the
diagram below illustrates 4 devices connected to the same TDM bus. While one DOUT pin is driving
data, the others will be tri-stated.
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PP Rev 3.0 December 2005
22