WM8986_07 Datasheet, PDF (18/87 Pages) Wolfson Microelectronics plc – Multimedia DAC With Class D Headphone and Line Out

WM8986
INTERNAL POWER ON RESET CIRCUIT
Pre-Production
Figure 7 Internal Power on Reset Circuit Schematic
The WM8986 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used to
reset the digital logic into a default state after power up. The POR circuit is powered from AVDD1
and monitors DCVDD. It asserts PORB low if AVDD1 or DCVDD is below a minimum threshold.
Figure 8 Typical Power up Sequence where AVDD1 is Powered before DCVDD
Figure 8 shows a typical power-up sequence where AVDD1 comes up first. When AVDD1 goes
above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is
asserted low and the chip is held in reset. In this condition, all writes to the control interface are
ignored. Now AVDD1 is at full supply level. Next DCVDD rises to Vpord_on and PORB is released high
and all registers are in their default state and writes to the control interface may take place.
On power down, where AVDD1 falls first, PORB is asserted low whenever AVDD1 drops below the
minimum threshold Vpora_off.
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PP, Rev 3.1, February 2007
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