WM8602 Datasheet, PDF (16/46 Pages) Wolfson Microelectronics plc – 2.1 CHANNEL PWM CONTROLLER

WM8602
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In DSP mode A or B, all channels are time multiplexed onto DIN. LRCLK is used as a frame sync
signal to identify the MSB of the first word. The minimum number of BCLKs per LRCLK period is 8
times the selected word length. Any mark to space ratio is acceptable on LRCLK provided the rising
edge is correctly positioned (see Figure 9, Figure 10 and Figure 11).
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCLK following a LRCLK
transition. LRCLK is high during the left samples and low during the right samples.
Figure 9 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK transition.
LRCLK is high during the left samples and low during the right samples.
Figure 10 Right Justified Mode Timing Diagram
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PP Rev 1.5 May 2004
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