WM2331 Datasheet, PDF (16/25 Pages) Wolfson Microelectronics plc – 10-bit 30MSPS ADC with PGA and Clamp

WM2331
Production Data
After power up, the clamp reference voltage is the voltage supplied on the CLAMPIN pin. However, it
can also be generated by the on-chip 10-bit clamp level DAC by suitably programming the WM2331
clamp and control registers (see Digital Control Registers, below).
Clamp design for minimum acquisition time and droop is discussed in Applications Information.
CLAMP DAC OUTPUT VOLTAGE RANGE AND LIMITS
Important: When using the internal clamp DAC in Top/Bottom or Centre Span Mode, the user must
ensure that the desired DC clamp level at AIN lies within the voltage range REFBF to REFTF. This is
because the clamp DAC voltage is constrained to lie within this range REFBF to REFTF. Specifically:
VDAC
= REFBF + (REFTF × íÃS@A7Aà (0.006 + 0.988×(DAC code)/1024)
DAC codes can range from 0 to 1023. Figure 18 shows the clamp DAC output voltage versus the
DAC code.
VDAC
VREFTF
VREFBF + 0.006(VREFTF-VREFBF)
VREFBF
0
VREFBF + 0.987(VREFTF-VREFBF)
1023
DAC
code
Figure 18 Clamp DAC Output Voltage versus DAC Register Code Value
If the desired DC level at AIN does not lie within the range REFTF to REFBF, then either:
• the CLAMPIN pin can be used instead to provide a suitable reference voltage or
• it may be possible to re-design the application to move the AIN input range into the
CLAMP DAC voltage range. This is achieved in both Top/Bottom and Centre Span
Modes by shifting both REFTS and REFBS up or down by the voltage through which
the AIN input range is to be moved.
POWER MANAGEMENT
In power-sensitive applications (such as battery-powered systems) where the WM2331 ADC is not
required to convert continuously, power can be saved between conversion intervals by placing the
WM2331 into Power Down mode. This is achieved by setting bit 3 (PDWN) of the control register to
1. In Power Down mode, the device typically consumes less than 3mW of power. Power down mode
is exited by resetting control register bit 3 to 0. On power up from long periods of power down, the
WM2331 typically requires 5ms of wake up time before valid conversion results are available.
In systems where the ADC must run continuously, but where the clamp is not required, the supply
current can be reduced by approximately 1.2mA by setting the control register bit 6 (CLDIS), which
disables the clamp circuit. Similarly, when REFSENSE is tied to AVDD, the reference generator is
disabled and supply current reduced by approximately 1.2mA.
OUTPUT FORMAT AND DIGITAL I/O
While the OEB pin is held low, ADC conversion results are output at the data I/O pins DIO0 (LSB) to
DIO9 (MSB). The default output data format is unsigned binary (output codes 0 to 1023). This can be
switched to two’s complement format (output codes -512 to 511) by setting control register bit 5
(TWOC) to 1.
WRITING TO THE INTERNAL REGISTERS THROUGH THE DIGITAL I/O BUS
Pulling the OEB pin high disables the data and out-of-range indicator (OVR) pins’ output drivers,
setting the driver outputs to a high impedance state. This allows control register data to be loaded
into the WM2331 by presenting it on the DIO0 to DIO9 pins and pulsing the WR pin high to latch the
data into the chosen control or DAC register.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.4 April 2001
16