WM8199_07 Datasheet, PDF (15/32 Pages) Wolfson Microelectronics plc – 20MSPS 16-bit CCD Digitiser

WM8199
C_IN
RINP
EXTERNAL VRLC
VRLC/
VBIAS
Production Data
RLC/ACYC MCLK VSMP
TIMING CONTROL
CL
R_S
V_S
FROM CONTROL
INTERFACE
2
1
RLC
S/H
S/H
CDS
CDS
4-BIT
RLC DAC
VRLCEXT
+
+
TO OFFSET DAC
-
INPUT SAMPLING
BLOCK FOR RED
CHANNEL
FROM CONTROL
INTERFACE
Figure 11 Reset Level Clamping and CDS Circuitry
If auto-cycling is not required, RLC can be selected by pin RLC/ACYC. Figure 12 illustrates control of
RLC for a typical CCD waveform, with CL applied during the reset period.
The input signal applied to the RLC/ACYC pin is sampled on the positive edge of MCLK that occurs
during each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the
internal CL pulse on the next reset level. The position of CL can be adjusted by using control bits
CDSREF[1:0] (Figure 13).
If auto-cycling is required, pin RLC/ACYC is no longer available for this function and control bit
RLCINT determines whether clamping is applied.
MCLK
VSMP
ACYC/RLC
or RLCINT
CL
(CDSREF = 01)
1
X
X
Programmable Delay
0
X
INPUT VIDEO
RGB
RGB
RLC on this Pixel
X
0
RGB
No RLC on this Pixel
Figure 12 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL
The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit
RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
CDS/NON-CDS PROCESSING
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this sets switch 2 into the position shown in (Figure 11) and causes the signal
reference to come from the video reset level. The time at which the reset level is sampled, by clock
Rs/CL, is adjustable by programming control bits CDSREF[1:0], as shown in Figure 13.
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PD Rev 4.3 March 2007
15