WM9707 Datasheet, PDF (14/30 Pages) Wolfson Microelectronics plc – AC97 Revision 2.1 Audio Codec with Spdif Output

WM9707
SYNC
BIT_CLK
TAG PHASE
12.288MHz
81.4nS
DATA PHASE
20.8µS (48kHz)
Advanced Information
SDATA_OUT
VALID
FRAME
SLOT(1)
SLOT(2)
SLOT(12) ’0’ (ID1) (ID0) 19
0
END OF PREVIOUS
AUDIO FRAME
TIME SLOT ’VALID’ BITS
(’1’ = TIME SLOT CONTAINS
VALID PCM DATA)
SLOT (1)
19
0
SLOT (2)
19
0
SLOT (3)
19
0
SLOT (12)
Figure 11 AC-link Audio Output Frame
The datastreams currently defined by the AC’97 specification include:
PCM playback - 2 output slots
PCM record data - 2 input slots
Control - 2 output slots
Status - 2 input slots
Optional modem line codec output -
1 output slot
Optional modem line codec input –
1 input slot
Optional dedicated microphone input -
1 input slot
2-channel composite PCM output stream
2-channel composite PCM input stream
Control Register write port
Control Register read port
Modem line codec DAC input stream
Modem line codec ADC output stream
Dedicated microphone input stream in support
of stereo AEC and/or other voice applications.
Synchronisation of all AC-link data transactions is signalled by the WM9707 controller. The WM9707
drives the serial bit clock onto AC-link, which the AC’97 controller then qualifies with a
synchronisation signal to construct audio frames.
SYNC, fixed at 48kHz, is derived by dividing down the serial clock (BIT_CLK). BIT_CLK, fixed at
12.288MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming
time slots. AC-link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-link
data, (WM9707 for outgoing data and AC’97 controller for incoming data), samples each serial bit on
the falling edges of BIT_CLK.
The AC-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid
tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0
indicates that the corresponding time slot within the current audio frame has been assigned to a data
stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the
data, (the WM9707 for the input stream, AC’97 controller for the output stream), to stuff all bit
positions with 0s during that slot’s active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame.
The portion of the audio frame where SYNC is high is defined as the Tag Phase. The remainder of
the audio frame where SYNC is low is defined as the Data Phase. Additionally, for power savings, all
clock, sync, and data signals can be halted. This requires that the WM9707 be implemented as a
static design to allow its register contents to remain intact when entering a power savings mode.
WOLFSON MICROELECTRONICS LTD
AI Rev 2.2 January 2001
14