WM8580A Datasheet, PDF (14/106 Pages) Wolfson Microelectronics plc – Multichannel CODEC with S/PDIF Transceiver

WM8580A
DIGITAL AUDIO INTERFACE – SLAVE MODE
PAIFTX_BCLK/
PAIFRX_BCLK/
SAIF_BCLK
t_BCH
t_BCL
t_BCY
PAIFTX_LRCLK/
PAIFRX_LRCLK/
SAIF_BCLK
DIN1/2/3/
SAIF_DIN
t_DS
t_DD
DOUT/
SAIF_DOUT
t_LRH
t_DH
t_LRSU
Production Data
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, PVDD = 5V, DVDD = 3.3V, AGND = 0V, PGND,DGND = 0V, TA = +25^oC, Slave Mode, fs = 48kHz, MCLK and
ADCMCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
PAIFTX_BCLK/
tBCY
PAIFRX_BCLK/SAIF_BCLK cycle
time
PAIFTX_BCLK/
tBCH
PAIFRX_BCLK/SAIF_BCLK pulse
width high
PAIFTX_BCLK/
tBCL
PAIFRX_BCLK/SAIF_BCLK pulse
width low
PAIFTX_LRCLK/
t_LRSU
PAIFRX_LRCLK/SAIF_BCLK set-up
time to PAIFTX_BCLK/
PAIFRX_BCLK/SAIF_BCLK rising
edge
PAIFTX_LRCLK/
t_LRH
PAIFRX_LRCLK/
SAIF_LRCLK hold time from
PAIFTX_BCLK/
PAIFRX_BCLK/SAIF_BCLK rising
edge
DIN1/2/3/SAIF_DIN set-up time to
t_DS
PAIFRX_BCLK/
SAIF_BCLK rising edge
DIN1/2/3/SAIF_DIN hold time from
tDH
PAIFRX_BCLK/SAIF_BCLK rising
edge
DOUT/SAIF_DOUT propagation
tDD
delay from
PAIFTX_BCLK/SAIF_BCLK falling
edge
Table 5 Digital Audio Data Timing – Slave Mode
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
10
ns
10
ns
10
ns
10
ns
0
10
ns
w
PD, Rev 4.9, November 2013
14