WM8728 Datasheet, PDF (13/28 Pages) Wolfson Microelectronics plc – 24-bit, 192kHz Stereo DAC with Volume Control and DSD Support

WM8728
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RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left data word and low during the right data word.
LRCIN
BCKIN
LEFT CHANNEL
1/fs
RIGHT CHANNEL
DIN
123
n-2 n-1 n
123
n-2 n-1 n
MSB
LSB
MSB
LSB
Figure 8 Right Justified Mode Timing Diagram
I²S MODE
In I²S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is low during the left data word and high during the right data word.
1/fs
LRCIN
LEFT CHANNEL
RIGHT CHANNEL
BCKIN
1 BCKIN
DIN
123
MSB
n-2 n-1 n
LSB
1 BCKIN
123
MSB
n-2 n-1 n
LSB
Figure 9 I²S Mode Timing Diagram
DSP EARLY MODE
In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that
detects a low to high transition on LRCIN. No BCKIN edges are allowed between the data words.
The word order is DIN left, DIN right.
LRCIN
BCKIN
DIN
1 BCKIN
1/fs
LEFT CHANNEL
RIGHT CHANNEL
12
MSB
n-1 n 1 2
LSB
Input Word Length (IWL)
n-1 n
1 BCKIN
NO VALID DATA
Figure 10 DSP Early Mode Timing Diagram
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
13