WM8569 Datasheet, PDF (12/36 Pages) Wolfson Microelectronics plc – 24-bit, 192kHz Stereo CODEC with Volume Control

WM8569
MPU INTERFACE TIMING
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Figure 6 SPI Compatible Control Interface Input Timing
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25^oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise
stated
PARAMETER
SYMBOL
MIN
SCLK/IWL rising edge to CSB/IDF rising edge
tSCS
60
SCLK/IWL pulse cycle time
tSCY
80
SCLK/IWL pulse width low
tSCL
30
SCLK/IWL pulse width high
tSCH
30
SDIN/DM to SCLK/IWL set-up time
tDSU
20
SCLK/IWL to SDIN/DM hold time
CSB/IDF pulse width low
tDHO
20
tCSL
20
CSB/IDF pulse width high
tCSH
20
CSB/IDF rising to SCLK/IWL rising
tCSS
20
Table 4 3-Wire SPI Compatible Control Interface Input Timing Information
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
w
PP Rev 1.1 December 2005
12