WM8523 Datasheet, PDF (12/51 Pages) Wolfson Microelectronics plc – 24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output

WM8523
AUDIO INTERFACE TIMING – SLAVE MODE
Production Data
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25^°C, Slave Mode
PARAMETER
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DACDAT hold time from LRCLK rising edge
DACDAT set-up time to BCLK rising edge
Table 2 Slave Mode Audio Interface Timing
SYMBOL
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
tDS
MIN
TYP
MAX
UNIT
27
ns
11
ns
11
ns
7
ns
5
ns
5
ns
7
ns
Note:
BCLK period should always be greater than or equal to MCLK period.
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PD, Rev 4.1, August 2011
12