WM8200 Datasheet, PDF (12/16 Pages) Wolfson Microelectronics plc – 40MSPS ADC with PGA

WM8200
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REGISTER MAP DESCRIPTION
REGISTER
Clamp
Register 1
Clamp
Register 2
PGA
Control
Register
Control
Register
BIT
BIT
DEFAULT
NAMES
DESCRIPTION
7:0
DAC[7:0] 00000000 Clamp DAC value bits 7 to 0 (Unsigned binary format)
1:0
DAC[9:8]
00
Clamp DAC value bits 9 to 8 (Unsigned binary format)
2:0
PGA[2:0]
001
4
PGAOFF
0
5 PGASENSE
0
0
PD
0
1
CLDIS
0
2
TWOSC
0
3
OEB
0
4
CLPSEL
0
PGA Gain control
000: PGA Gain = 0.5x
100: PGA Gain = 2.5x
001: PGA Gain = 1.0x
101: PGA Gain = 3.0x
010: PGA Gain = 1.5x
110: PGA Gain = 3.5x
011: PGA Gain = 2.0x
111: PGA Gain = 4.0x
Enables a coarse offset to be added to the output of the PGA. Allows the
use of single ended input signals with no loss of ADC dynamic range.
Determines the sense of the coarse offset added to the output of the PGA.
This bit only has an effect when PGAOFF=1.
0: PGA output is offset to full-scale positive for zero differential input
(suitable for negative going video).
1: PGA output is offset to full-scale negative for zero differential input
(suitable for positive going video).
Device power-down
0: Device is powered up
1: Device is powered down.
CLAMP amplifier enable (for power saving)
0: Enable
1: Disable
Output data format
0: Unsigned binary
1: Twos complement
Output data pin enable
0: DO[9:0]/DO[11:0] enabled
1: DO[9:0]/DO[11:0] disabled (outputs are high impedance).
Clamp source select
0: Clamp to output of Clamp DAC
1: Clamp to voltage on AINN input pin
POWER MANAGEMENT
In power-sensitive applications (such as battery-powered systems) where the WM8200 ADC is not
required to convert continuously, power can be saved between conversion intervals by placing the
WM8200 into Power Down mode. This is achieved by setting bit 0 (PD) of the control register to 1. In
Power Down mode, the device typically consumes less than 3mW of power. Power down mode is
exited by resetting control register bit 1 to 0. On power up from long periods of power down, the
WM8200 typically requires 5ms of wake up time before valid conversion results are available.
In systems where the ADC must run continuously, but where the clamp is not required, the supply
current can be reduced by approximately 1.2mA by setting the control register bit 1 (CLDIS), which
disables the clamp circuit. Similarly, when REFSENSE is tied to AVDD, the reference generator is
disabled and supply current reduced by approximately 1.2mA.
DATA OUTPUT FORMAT
While the OEB pin is held low, ADC conversion results are output at the data I/O pins DO[0] (LSB) to
DO[9] (MSB). The default output data format is unsigned binary (output codes 0 to 1023). This can
be switched to two’s complement format (output codes -512 to 511) by setting control register bit 2
(TWOSC) to 1.
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PP Rev 1.22 March 2002
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