WM8738 Datasheet, PDF (11/15 Pages) Wolfson Microelectronics plc – 24 BIT STEREO ADC

WM8738
Production Data
DIGITAL AUDIO INTERFACES
The WM8738 has two data output formats, selectable via the FMT pin.
FMT = 0 ADC audio data output is I²S
FMT = 1 ADC audio data output is Left Justified
Both of these modes are MSB first.
The digital audio interface takes the data from the internal ADC digital filter. SDATO is the formatted
digital audio data stream output from the ADC digital filters with left and right channels multiplexed
together. LRCLK is an alignment clock that controls whether Left or Right channel data is present on
the SDATO line. SDATO and LRCLK are synchronous with the BCLK signal with each data bit
transition signified by a low to high BCLK transition.
LEFT JUSTIFIED MODE
In left justified mode, the MSB of the ADC data is output on SDATO and changes on the same falling
edge of BCLK as LRCLK and may be sampled on the rising edge of BCLK. LRCLK is high during
the left samples and low during the right samples.
LRCLK
BCLK
1/fs
L EF T C H AN N EL
R IGH T C H AN N EL
SD ATO
12 3
M SB
n-2 n-1 n
LSB
123
M SB
Figure 4 Left Justified Mode Timing Diagram
n-2 n-1 n
LSB
I²S MODE
In I²S mode, the MSB of the ADC data is output on SDATO and changes on the first falling edge of
BCLK following an LRCLK transition and may be sampled on the rising edge of BCLK. LRCLK is low
during the left samples and high during the right samples.
1/fs
LRCLK
LEFT C H AN N EL
R IGH T C H AN N EL
BCLK
SD ATO
1 BCLK
123
M SB
n-2 n-1 n
LSB
Figure 5 I²S Mode Timing Diagram
1 BCLK
123
M SB
n-2 n-1 n
LSB
w
PD Rev 4.3 November 2004
11