WM8524 Datasheet, PDF (10/25 Pages) Wolfson Microelectronics plc – 24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output

WM8524
POWER ON RESET CIRCUIT
Production Data
Figure 3 Internal Power on Reset Circuit Schematic
The WM8524 includes an internal Power-On-Reset circuit, as shown in Figure 3, which is used to
reset the DAC digital logic into a default state after power up. The POR circuit is powered by AVDD
and has as its inputs VMID and LINEVDD. It asserts POR low if VMID or LINEVDD are below a
minimum threshold.
Figure 4 Typical Power Timing Requirements
Figure 4 shows a typical power-up sequence where LINEVDD comes up with AVDD. When AVDD
goes above the minimum threshold, V_pora, there is enough voltage for the circuit to guarantee POR is
asserted low and the chip is held in reset. In this condition, all writes to the control interface are
ignored. After VMID rises to V_{pord_hi} and AVDD rises to V_{pora_hi,} POR is released high and all registers
are in their default state and writes to the control interface may take place.
On power down, PORB is asserted low whenever LINEVDD or AVDD drop below the minimum
threshold V_{pora_low}.
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PD, Rev 4.1, October 2011
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