WM8501_09 Datasheet, PDF (10/20 Pages) Wolfson Microelectronics plc – 24-bit 192kHz Stereo DAC with 1.7Vrms Line Driver

WM8501
CLOCKING SCHEMES
Production Data
In a typical digital audio system there is only one central clock source producing a reference clock
to which all audio data processing is synchronised. This clock is often referred to as the audio
system’s Master Clock. The external master clock can be applied directly through the MCLK input
pin with no configuration necessary for sample rate selection.
Note that on the WM8501, MCLK is used to derive clocks for the DAC path. The DAC path
consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In
a system where there are a number of possible sources for the reference clock it is recommended
that the clock source with the lowest jitter be used to optimise the performance of the DAC.
The device can be powered down by stopping MCLK. In this state the power consumption is
substantially reduced.
DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Three interface
formats are supported:
• Right Justified mode
• I²S mode
• DSP mode
All formats send the MSB first. The data format is selected with the FORMAT pin. When
FORMAT is LOW, right justified data format is selected and word lengths of 16-bits may be used.
When the FORMAT pin is HIGH, I²S format is selected and word length of any value up to 24-bits
may be used. (If a word length shorter than 24-bits is used, the unused bits should be padded
with zeros). If LRCLK is 4 BCLKs or less duration, the DSP compatible format is selected. Mode
A and Mode B clock formats are supported, selected by the state of the FORMAT pin.
‘Packed’ mode (i.e. only 32 or 48 clocks per LRCLK period) operation is also supported in both
I²S (16-24 bits) and right justified formats, (16 bit). If a ‘packed’ format of 16-bit word length is
applied (16 BCLKS per LRCLK half period), the device auto-detects this mode and switches to
16-bit data length.
I²S MODE
The WM8501 supports word lengths of 16-24 bits in I²S mode.
In I²S mode, the digital audio interface receives data on the DIN input. Audio Data is time
multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also used
as a timing reference to indicate the beginning or end of the data words.
In I²S modes, the minimum number of BCLKs per LRCLK period is 2 times the selected word
length. LRCLK must be high for a minimum of word length BCLKs and low for a minimum of word
length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the above requirements
are met. In I²S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK
transition. LRCLK is low during the left samples and high during the right samples.
Figure 3 I²S Mode Timing Diagram
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PD, Rev 4.2, July 2009
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