WS74HC164 Datasheet, PDF (1/5 Pages) Wing Shing Computer Components – 8-Bit Serial-in/Parallel-out Shift Register

WS74HC164
8-Bit Serial-in/Parallel-out Shift Register
GENERAL DESCRIPTION
74HC164 is fabricated in the high-speed silicon
gate CMOS technology. It has the high noise
immunity and low power consumption of standard
CMOS integrated circuits. It also offers speeds
comparable to low power Schottky devices
(LS-TTL).
This 8-bit Shift Register has AND-gated serial
inputs and clear. Each register bit is a D-type
master-slave flip-flop. Inputs A & B permit
complete control over the incoming data. A low at
either or both inputs inhibits entry of new data and
resets the first flip-flop to the low level at the next
clock pulse. A high level on one input enables
another input, which will then determine the state
of the first flip-flop. Data at the serial inputs may be
changed while the clock is high or low, but only
data meeting the setup and hold time requirements
will be entered. Data is serially shifted in and out of
the 8-bit register during the positive edge of the
clock pulse. Clear is independent of the clock and
accomplished by a low level at the clear (CL) input.
74HC164 logic is functionally as well as pin-out
compatible with the standard LS164. All inputs are
protected from ESD damage by internal diode
clamps to Vcc and ground.
FEATURES
• Wide operating supply voltage range: 2-6V.
• Asynchronous master reset CL active at low
• Date serially shifted at the positive edge of clock CK
• Low input current: < 1µA.
• Low quiescent supply current: 80µA maximum
• Output driving capability: standard
LOGIC DIAGRAM
A
B
Q1
Q2
Q3
Q4
GND
1
14
WS74HC164
7
8
VCC
Q8
Q7
Q6
Q5
CL
CK
8
CK
SERIAL _A ¹
INPUTS _B ²
9
CL
CK CK
D
Q
CL
CK CK
D
Q
CL
CK CK
D
Q
CL
CK CK
D
Q
CL
CK CK
D
Q
CL
CK CK
D
Q
CL
CK CK
D
Q
CL
CK CK
D
Q
CL
Q₁
Q₂
Q₃
Q₄
Q₅
Q₆
Q₇
Q₈
3
4
5
6
10
11
12
13
FUNCTIONAL DESCRIPTION
1. Truth Table
Inputs
CL
CK
AB
Q1
L
X
XX
L
H
L
XX
Q1O
H
↑
HH
H
H
↑
LX
L
H
↑
XL
L
Outputs
Q2 … Q8
L
L
Q2O
Q8O
Q1N
Q7N
Q1N
Q7N
Q1N
Q7N
H = High Level (steady state). L= Low Level (steady state)
X = don’t care (any input, including transitions)
↑= Transition from low to high level.
Q1O , Q2O , Q8O = the level of Q1 , Q2 , Q8 , respectively, before the indicated steady state input conditions
were established.
Q1N , Q7N = The level of Q1 or Q7 before the most recent ↑ transition of the clock; indicates a one-bit shift.
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