W83320S Datasheet, PDF (8/18 Pages) Winbond – N-Channel FET Synchronous Buck Regulator Controller

W83320S/W83320G
Soft-Start
When V_DDA and V_DD ramp over 4.3V and the voltage at pin V_REF ramps over 0.27V; the soft start
capacitor begins to charge through an internal 12uA (I_REF/2) current source. The error amplifier (and
the PWM duty) is both output clamped by the voltage on soft-start pin V_SS and input clamped by the
voltage on V_REF. There are two ways to soft start the power that’s following the rising of the slower one
between V_SS or V_REF; during soft-start, PWOK is forced to low and the internal Over-Current Protection
is triggered to work. 0.4V to 1.9V of V_SS is roughly mapping to 0 to 100% pulse-width. Smaller than
0.27V on V_REF will disable the PWM controller and discharge C_SS.
MOSFET Gate Drivers
The power for the high-side driver is flowing through the BOOT pin. This voltage can be supplied by a
separate, higher voltage source, or supplied from a local charge pump structure or combination of the
two.
Since the voltage of the low-side MOSFET gate and the high-side MOSFET gate are being monitored
to determine the state of the MOSFET, it should be taken carefully to add external components
between the gate drivers and their respective MOSFET gates. Doing so may interfere with the shoot-
through protection.
Current Limit
Current limit is implemented by sensing the voltage across the low-side MOSFET while it is ON. This
method enhances the converter's efficiency and reduces total cost by eliminating a current sensing
resistor.
While low-side MOSFET is turned on, a constant current of 72uA (IREF X 3) is forced through
ROCSET which is an external resistor connected between phase and ISEN, causing a fixed voltage
drop. This fixed voltage is compared against VDS and if the latter is higher, the chip enters current
limit mode. In the current limit mode both the high-side and low-side MOSFETS are turned off and the
soft start capacitor CSS will be discharged immediately. The VREF is shorted to GND for 5~10uS to
indicate the over current condition. After a 5mS delay, a soft-start cycle is initiated. If the cause of the
over-current is still present after the delay interval, the current limit would be triggered again. The shut
down - delay - soft start cycle will be repeated indefinitely until the over-current event been removed.
Input Tracking
When the VREF voltage is less than 0.3V, the PWM is shut-down and the UGATE and LGATE are
driven low. Due to its wide input range (0 ~ 3.6V), this chip is suitable for reference input tracking
application. But note that the chip will be shut-down when VREF <0.27V, a proper setting of CSS is
needed to clamp the output at initiation of start up and avoid output voltage step-up ( and so a large
inrush current).
I_REF and PWM Clock
The Internal reference current (IREF) is determined by the resistor between pin BG_REF pin and
GND (RSET) according to the following equation:
I_REF = 1.19V/Rset
The nominal 200 kHz PWM clock can be adjusted ranging form 100 kHz to 400 kHz by changing IREF
according to the following equation:
Freq = 200 KHz * I_REF / 24uA;
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