W536020K Datasheet, PDF(8/16 Page) Winbond – VOICE/MELODY/LCD CONTROLLER (ViewTalk TM Series)

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W536020K Datasheet, PDF (8/16 Pages) Winbond – VOICE/MELODY/LCD CONTROLLER (ViewTalk TM Series)

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W536020K/030K/060K/090K/120K

PAD Description, continued

SYMBOL

COM0âCOM3

COM4/PORTO.0

ï£¦

COM7/PORTO.3

DH1, DH2 (6)

VHI

V5 V6 (6)

V2 (6)

VSSP (7)

VSS (7)

VDDP (7)

VDD (7)

I/O

FUNCTION

LCD common signal output pads either 1/8 duty or 1/4duty. The LCD

O frame rate is controlled by LCDM1 register, and default value LCDM1 =

0111b with 64Hz frame rate.

LCD common signal output pads, or shared as general input by register

O/I LCDM3.2 when in 1/4 duty mode. Default function is common function

and PM5.2 = 0 to inhibit LCD waveform abnormal.

Connection terminal for voltage double capacitor with 0.1uF. The DH2

O connects to capacitor positive node and DH1 negative node if polar

capacitor is used.

Connect to V6 (LCD's VLCD) or VDD which has higher voltage, to make

sure there is no any abnormal leakage current appearance.

LCD COM/SEG output driving voltage. Need an external 0.1uF

capacitor when 1/4 bias. (LCDM0.1 = 1)

LCD COM/SEG output driving voltage. Need an external 0.1uF

capacitor to every pad terminal.

Voltage regulator output pad. An external capacitor is a must. Output

level can be controlled from 0~Fh by LCDM4 register. If internal pump is

enabled (LCDM3.3 = 0 and default value), LCD operating voltage

I/O

(VLCD) will be 3*V2 or 4*V2 depending on 1/3 bias or 1/4 bias. A

limitation should be noted that VLCD must be higher than (VDD -0.5v) to

avoid chip leakage current. While external reference voltage is selected

(LCDM3.3 = 1), V2 pad input voltage can not be over 1.5 Volt to inhibit

chip damage.

I Power ground for PWM or DAC playing output.

I Power ground

I Power source for PWM or DAC playing output.

I Power Source

Notes:

(4) RD1~3 are shared as CLK/DATA/ADDR to interface with W55XXX @W536020K/030K.

(5) @W536120K only

(6) 0.1uF is default value, and capacitor value should be larger than 0.1uF if LCD dot size over 0.5mm * 0.5mm.

(7) External application circuit should connect together, please refer to APPLICATION CIRCUIT. To sure chip operation

properly, please bond all VDD, VDDP, VSS and VSSP pads and connect VSS and VSSP from chip outside PCB circuit.

(8) VHI pad is bonded to V6 or VDD.

(9) When working at NMOS open drain mode, external pull high voltage can't bigger than VDD to avoid leakage current.

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