W83304D Datasheet, PDF (7/16 Pages) Winbond – ACPI Controller For AMD Claw Hammer TM CPU

W83304D/W83304G
Pin Descriptions, continued
NO NAME
I/O
POWER
SOURCE
FUNCTION DESCRIPTION
8
V_DD_GD
CPU Power Good Signal.
I
5VSB
The signal is inputted for power sequence control.
Signal Output to Enable CPU Power.
9
V_DD_EN
OD₂₄
5VSB
The signal output to enable CPU power for sequence control.
10
V_CC3
P
Power V_CC.
11 2.5V_DDA AO_200mA VCC3 2.5V Power for CPU PLL Core.
12
GND
P
Power Ground.
13 1.25V_REF AO_5mA 3VSB 1.25V Reference Voltage.
Soft-Start Pin.
14
SS
AI/AO 5VSB _{A capacitor (0.1u) is attached in this pin for soft-start slope}
rate adjustment.
Reference Current Input.
15
I_SET
AI/AO 5VSB _{An input current for internal circuit reference.}
16 V_TT_SINK
AO
5VSB _{Power VTT.}
17 V_TT_SEN
AI
5VSB A bi-direction linear regulator is provided to regulate voltage
18 V_TT_DRV
AO
9VSB ^{for DDR bus terminator.}
19 V_DDIO_SEN
AI
20
I_SEN2
AI
21 V_DDIO_DRV2 AO
22
I_SEN1
AI
23 V_DDIO_DRV1 AO
9VSB
Power V_DDIO.
A dual-channels linear regulator with current balancing
architecture is provided for higher current DDR SDRAM
application.
24
GND
P
Power Ground.
25 V_LDT_SEN
AI
5VSB _{Power VLDT.}
26 V_LDT_DRV
AO
9VSB ^{1.2V power for LDT bus.}
27
5V_SB
P
Standby Power Pin.
28 LR2_SEN
AI
5VSB Linear Regulator 1.
A general purpose linear regulator is provided to generate
29 LR2_DRV
AO
9VSB _{1.2V~5.0V power for specific device.}
30 LR1_SEN
AI
5VSB Linear Regulator 2.
A general purpose linear regulator is provided to generate
31 LR1_DRV
AO
9VSB _{1.2V~5.0V power for specific device.}
Publication Release Date: April, 2006
-7-
Revision 0.51