W523SXX Datasheet, PDF (7/14 Pages) Winbond – HIGH FIDELITY PowerSpeech-TM

W523SXX (PRELIMINARY)
Interrupt Vector Allocation
The W523Sxx provides a total of 4 trigger inputs to communicate with the outside world. Each trigger
pin can invoke 2 dedicate interrupt vectors depending on TG pins’ status (rising or falling). The table
below shows the relationship between triggers’ status and interrupt vectors.
INTERRUPT VECTOR
0
1
8
9
INTERRUPT VECTOR
4
5
12
13
32
TRIGGER SOURCE
TG1F
TG2F
TG5F
TG6F
TRIGGER SOURCE
TG1R
TG2R
TG5R
TG6R
POI
CPU Interface
The W523Sxx can communicate with an external microprocessor through a simple serial CPU
interface. The CPU interface consists of TG1, TG2 and STPA/BUSY pins, which are shown below:
TG1
(Data)
TG2
(Clock)
STPA/Busy
TDEB
Debounced OK. to clear the internal CPU
counter for preventing the system from
running away. (TG1F should be disabled.)
TCRD
END
AUD/SPK+
Note:
1. TDEB means the "Debounce time".
2. TCRD is the "CPU Reset Delay" time. This should be more than 2.6 µS.
3. The "Clock" frequency of the TG2 pin can be set in the range: 10 KHz - 1 MHz.
Busy signal will output "high" after the end of transmission. The rising timing of Busy signal is
Publication Release Date: Oct 2000
-7-
Revision A5