|
W972GG6JB-25 Datasheet, PDF (62/87 Pages) Winbond – Double Data Rate architecture: two data transfers per clock cycle | |||
|
◁ |
W972GG6JB
DQS
DQS
VDDQ
tDS tDH
VIH(ac)min
VREF to AC
region
VIH(dc)min
VREF(dc)
VIL(dc)max
nominal
slew rate
VIL(ac)max
tDS tDH
nominal
slew rate
VREF to AC
region
VSS
ÎTF
ÎTR
Setup Slew Rate
Falling Signal
=
VREF(dc) - VIL(ac)max
ÎTF
Setup Slew Rate
Rising Signal
VIH(ac)min - VREF(dc)
=
ÎTR
Figure 24 â Illustration of nominal slew rate for tDS (differential DQS, DQS )
- 62 -
Publication Release Date: Nov. 29, 2011
Revision A02
|
▷ |