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W25Q257FVEIF-TR Datasheet, PDF (61/104 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI | |||
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W25Q257FV
8.2.24 Set Burst with Wrap (77h)
In Standard SPI mode, the Set Burst with Wrap (77h) instruction is used in conjunction with âFast Read
Quad I/Oâ and âWord Read Quad I/Oâ instructions to access a fixed length of 8/16/32/64-byte section
within a 256-byte page. Certain applications can benefit from this feature and improve the overall system
code execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low
and then shifting the instruction code â77hâ followed by 24/32 dummy bits and 8 âWrap Bitsâ, W7-0. The
instruction sequence is shown in Figure 28. Wrap bit W7 and the lower nibble W3-0 are not used.
W6, W5
00
01
10
11
W4 = 0
Wrap Around
Wrap Length
Yes
8-byte
Yes
16-byte
Yes
32-byte
Yes
64-byte
W4 =1 (DEFAULT)
Wrap Around Wrap Length
No
N/A
No
N/A
No
N/A
No
N/A
Once W6-4 is set by a Set Burst with Wrap instruction, all the following âFast Read Quad I/Oâ and âWord
Read Quad I/Oâ instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any
page. To exit the âWrap Aroundâ function and return to normal read operation, another Set Burst with
Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on or after a
software/hardware reset is 1.
In QPI mode, the âBurst Read with Wrap (0Ch)â instruction should be used to perform the Read operation
with âWrap Aroundâ feature. The Wrap Length set by W5-4 in Standard SPI mode is still valid in QPI
mode and can also be re-configured by âSet Read Parameters (C0h)â instruction. Refer to 8.2.44 and
8.2.45 for details.
/CS
CLK
Mode 3
Mode 0
IO0
IO1
IO2
IO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3
Instruction (77h)
don't
care
don't
care
don't
care
Wrap Bit
Mode 0
X X X X X X w4 X
X X X X X X w5 X
X X X X X X w6 X
XXXXXXXX
Figure 28. Set Burst with Wrap Instruction (SPI Mode only)
32-Bit dummy bits are required when the device is operating in 4-Byte Address Mode
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Publication Release Date: November 13, 2015
Preliminary -Revision D
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