W83792AD Datasheet, PDF (43/97 Pages) Winbond – H/W Monitoring IC (CSB Version)

W83792AD/AG/D/G
Limit RAM setups the high/low limit for each channel in Value RAM. While exceeding these limits,
system will take certain action determined by prior setups.
FAN Count high limits should be the limit for lowest fan speed. This is because the slower the fan is,
the more the internal clock will be counted by internal clock.
Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means
interrupt will never be generated except the case when voltages go below the low limits.
VcoreA Limit Setup
CR[2B/2C] = [Desired Voltage]/0.008;
VcoreB Limint Setup
CR[2D/2E] = [Desired Voltage]/0.008;
VIN0~VIN3 Limit Setup
CR[2F~36] = [Desired Voltage] / 0.016;
5VCC Limit Setup
CR[37/38] = [Desired Voltage] / 0.024;
8.8 Configuration Register ⎯ Index 40h (Bank 0)
MNEMONIC BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Configuration 0
40 RW ^{INIT IRQEDGE IRQPOL ENWDT INT_CLR EN_IRQ EN_SMI START}
0
0
0
0
0
0
0
1
Reset Condition: Resume Reset, INIT.
Configuration Register controls the system reset, stop, power down and warning output mode.
BIT
NAME
7 ^{Initialization}
6 ^{IRQ output}
5 IRQ
Polarity
ATTRIBUTE
R/W
R/W
R/W
DESCRIPTION
Set one restores power on default value to all registers except
the Serial Bus Address register. This bit clears itself since the
power on default is zero.
Set 0 , IRQ output level signal . Set 1, output 200 us pulse
signal. Default is 0.
When set to 0, IRQ active high. Set to 1, IRQ active low.
Default is 0.
4 ENWDT
R/W
Set this bit to 1 will enable Watch Dog Timer function. Watch
dog timer function will reset system(pin 47) while it timeouts.
3 INT_Clear
R/W
A one disables the SMI# and IRQ# outputs without affecting
the contents of Interrupt Status Registers. The device will stop
monitoring at last channel. It will resume upon clearing of this
bit.
Note: The outputs of Interrupt pins will not be cleared if the
user writes a zero to this location after an interrupt has
occurred unlike "INT_Clear'' bit.
- 37 -
Publication Release Date: April 26, 2006
Revision 0.9