W9751G6JB-25 Datasheet, PDF (41/87 Pages) Winbond – 8M x 4 BANKS x 16 BIT DDR2 SDRAM

W9751G6JB
Operating Burst Read Current
All banks open, Continuous burst reads, IOUT = 0 mA;
BL = 4, CL = CL(IDD), AL = 0;
IDD4R ^{tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD);}
165
140
125
mA
1,2,3,4,5,
6
CKE is HIGH, CS is HIGH between valid commands;
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
Operating Burst Write Current
All banks open, Continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
IDD4W ^{tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD);}
200
165
150
mA
1,2,3,4,5,
6
CKE is HIGH, CS is HIGH between valid commands;
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
Burst Refresh Current
tCK = tCK(IDD);
Refresh command every tRFC(IDD) interval;
IDD5B _{CKE is HIGH, CS is HIGH between valid commands;}
105
95
90
mA
1,2,3,4,5,
6
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
Self Refresh Current
IDD6
CKE≤ 0.2 V, external clock off, CLK and CLK at 0 V;
Other control and address inputs are FLOATING;
6
6
6
mA
1,2,3,4,5,
6,7
Data bus inputs are FLOATING. (TCASE ≤ 85°C)
Operating Bank Interleave Read Current
All bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD(IDD) - 1 x tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD
IDD7
= tRCD(IDD);
245
200
180
mA
1,2,3,4,5,
6
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are STABLE during deselects;
Data Bus inputs are SWITCHING.
Notes:
1. VDD = 1.8 V  0.1V; VDDQ = 1.8 V  0.1V.
2. IDD specifications are tested after the device is properly initialized.
3. Input slew rate is specified by AC Parametric Test Condition.
4. IDD parameters are specified with ODT disabled.
5. Data Bus consists of DQ, LDM, UDM, LDQS, LDQS , UDQS and UDQS .
6. Definitions for IDD
LOW = Vin ≤ VIL (ac) (max)
HIGH = Vin ≥ VIH (ac) (min)
STABLE = inputs stable at a HIGH or LOW level
FLOATING = inputs at VREF = VDDQ/2
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
7. The following IDD values must be derated (IDD limits increase), when TCASE ≥ 85°C IDD2P must be derated by 20%;
IDD3P(slow) must be derated by 30% and IDD6 must be derated by 80%. (IDD6 will increase by this amount if TCASE < 85°C
and the 2X refresh option is still enabled)
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Publication Release Date: Nov. 29, 2011
Revision A05