W78IE52 Datasheet, PDF (4/22 Pages) Winbond – 8 BIT MICROCONTROLLER

Preliminary W78IE52
5. BLOCK DIAGRAM
P1.0
~
Port
P1.7
1
Port 1
Latch
INT2
INT3
Interrupt
Timer
2
Timer
0
Timer
1
UART
P3.0
~
Port
P3.7
3
Port 3
Latch
ACC
T1
B
T2
PSW
Stack
ALU
Pointer
Instruction
Decoder
&
Sequencer
SFR RAM
Address
256 bytes
RAM & SFR
Port 0
Latch
DPTR
Temp Reg.
PC
Incrementor
Addr. Reg.
P4.0
~
Port
P4.3
4
Port 4
Latch
Bus & Clock
Controller
ROM
Watchdog
Timer
Oscillator
Reset Block
Power control
Port 2
Latch
XTAL1 XTAL2 ALE PSEN RST
Vcc
Vss
P0.0
Port
0
~
P0.7
P2.0
Port
2
~
P2.7
6. FUNCTIONAL DESCRIPTION
The W78IE52 architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.
RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.
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