W536030A Datasheet, PDF (4/12 Pages) Winbond – VOICE/ MELODY / LCD CONTROLLER

  

PAD DESCRIPTION
SYMBOL
I/O
XIN/RXIN
I
XOUT
O
X32I/RSUB1
I
X32O/RSUB2
O
RA0 ~ RA3/TONE I/O
RB0 ~ RB3
I/O
RC0 ~ RC3
I
RD0
I
RD1/RDP
RD2/SPDATA
RD3/WRP
(4)
RE0~RE3
O
RF0~RF3
O
RES
I
FUNCTION
Input pad for main clock oscillator. It can be connected to crystal when crystal
mode is selected (SCR0.2=1), otherwise connect a resistor to VDD to generate
main system clock while RC mode is selected (SCR0.2=0 and default). Oscillator
can be enabled or stopped by set SCR0.1 to 1 or clear to 0 separately. External
capacitor connects to start oscillation while crystal mode
Output pad for oscillator which is connected to another crystal pad when in crystal
mode. External capacitor connects to start oscillation when in crystal mode.
32.768 KHz crystal input pad or external resistor node 1 by mask option.
External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.
32.768 KHz crystal output pad or external resistor node 2 by mask option.
External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.
General Input/Output port specified by PM1 register. If output mode is selected,
PM0 register bit 0 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode. RA3 may be uses as TONE if bit 0 of MR0 special
register is set to logic 1. An interrupt source.
General Input/Output port specified by PM2 register. If output mode is selected,
PM0 register bit 1 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode (W536060A/090A/120A only.)
4-bit sch
mitter input with internal pull high option specified by PM3 register bit 2. Each pad
has an independent interrupt capability specified by PEFL special register.
Interrupt and STOP mode wake up source. RC0 is also the external event
counter source of Timer1.
4-bit schmitter input port with internal pull high option specified by PM3 register
bit 3. Each pad has an independent interrupt capability specified by PEFH
special register. Interrupt and STOP mode wake up source. RD1~3 will be
shared as the external memory W55XXX interface pads while RD port shared as
serial bus mask option is enabled @W536030A/060A.
For W536030A/060A only, "Tri-state serial bus" mask option can use to float
WRP/RDP/SPDATD while "RD port shared as serial bus" mask option is
enabled.
Output port only. PM3 register bit 0 can be used to specify CMOS/NMOS driving
capability option. (W536090A/120A only)
Output port only. PM3 register bit 1 can be used to specify CMOS/NMOS driving
capability option. (W536090A/120A only)
System reset pad, active low with internal pull-high resistor.
Publication Release Date:April 2000
-4-
Revision A6