W9725G8JB Datasheet, PDF (31/86 Pages) Winbond – 8M  4 BANKS  8 BIT DDR2 SDRAM

W9725G8JB
8. OPERATION MODE
8.1 Command Truth Table
COMMAND
CKE
BA1
Previous Current _BA0
Cycle
Cycle
Bank Activate
H
H
BA
A12
A11
A10 A9-A0 _{CS RAS CAS WE} NOTES
Row Address
L
L
H
H
1, 2
Single Bank
Precharge
H
H
BA
X
L
X
L
L
H
L
1, 2
Precharge All
Banks
H
H
X
X
H
X
L
L
H
L
1
Write
H
H
BA Column L Column L
H
L
L 1, 2, 3
Write with
Auto-precharge
H
H
BA Column H Column L
H
L
L 1, 2, 3
Read
H
H
BA Column L Column L
H
L
H 1, 2, 3
Read with
Auto-precharge
H
H
BA Column H Column L
H
L
H 1, 2, 3
(Extended)
Mode Register
H
Set
H
BA
OP Code
L
L
L
L
1, 2
No Operation
H
X
X
X
X
X
L
H
H
H
1
Device
Deselect
H
Refresh
H
Self Refresh
Entry
H
Self Refresh
Exit
L
Power Down
Mode Entry
H
X
X
X
X
X
H
X
X
X
1
H
X
X
X
X
L
L
L
H
1
L
X
X
X
X
L
L
L
H
1, 4
H
X
X
X
H
X
X
X
X
1, 4, 5
L
H
H
H
H
X
X
X
L
X
X
X
X
1, 6
L
H
H
H
Power Down
Mode Exit
L
H
X
X
X
H
X
X
X
X
1, 6
L
H
H
H
Notes:
1. All DDR2 SDRAM commands are defined by states of CS , RAS , CAS , WE and CKE at the rising edge of the clock.
2. Bank addresses BA [1:0] determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
3. Burst reads or writes at BL = 4 can not be terminated or interrupted. See Burst Interrupt in section 7.5 for details.
4. V_REF must be maintained during Self Refresh operation.
5. Self Refresh Exit is asynchronous.
6. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the
refresh requirements outlined in section 7.9.
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Publication Release Date: Oct. 12, 2010
Revision A01