W83194AR-WE Datasheet, PDF (3/16 Pages) Winbond – 200MHZ CLOCK FOR WHITNEY CHIPSET

W83194AR-We
4.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kΩ pull-up
4.1 Crystal I/O
PRELIMINARY
SYMBOL
Xin
Xout
PIN
I/O
FUNCTION
3
IN Crystal input with internal loading capacitors(36pF)
and feedback resistors.
4
OUT Crystal output at 14.318MHz nominally with internal
loading capacitors(36pF).
4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
SYMBOL
CPUCLK [0:1]
PD#
IOAPIC
SDRAM [ 0:8]
PCICLK0/ *FS0
PCICLK1/ FS1#
PCICLK2/ *FS2
PCICLK3/*APIC_SEL
PCICLK [ 4:7 ]
3V66 [0:1]
PIN
45,44
29
47
41,40,
39,37,36,35,33
,32,31
10
11
12
14
15,17,18,19
7,8
I/O
OUT
IN
OUT
OUT
I/O
I/O
I/O
I/O
OUT
OUT
FUNCTION
Low skew (< 250ps) clock outputs for host
frequencies such as CPU and Chipset.
Power Down mode when driven low.
Clock outputs synchronous with PCI clock and
powered by VddA.
SDRAM clock outputs.
3.3V 33MHz PCI clock during normal operation.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks(Default=1).
Low skew (< 250ps) PCI clock outputs.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks(Default=0).
Low skew (< 250ps) PCI clock outputs.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks(Default=1).
Low skew (< 250ps) PCI clock outputs.
Latched input for APIC_SEL at initial power up for
H/W selecting the output frequency of IOAPIC clock
(Default=1).
Low skew (< 250ps) PCI clock outputs.
3.3V output clocks for the chipset.
Publication Release Date: Nov. 1999
-3-
Revision 0.50