W78E516B_06 Datasheet, PDF (25/37 Pages) Winbond – 8-BIT MICROCONTROLLER

W78E516B
7.3.3 Data Read Cycle
PARAMETER
ALE Low to RD Low
RD Low to Data Valid
Data Hold from RD High
Data Float from RD High
RD Pulse Width
SYMBOL
TDAR
TDDA
TDDH
TDDZ
TDRD
MIN.
3 TCP-Δ
-
0
0
6 TCP-Δ
Notes:
1. Data memory access time is 8 TCP.
2. "Δ" (due to buffer driving delay and wire loading) is 20 nS.
TYP.
-
-
-
-
6 TCP
MAX.
3 TCP+Δ
4 TCP
2 TCP
2 TCP
-
UNIT
nS
nS
nS
nS
nS
NOTES
1, 2
1
2
7.3.4 Data Write Cycle
PARAMETER
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
SYMBOL
TDAW
TDAD
TDWD
TDWR
Note: "Δ" (due to buffer driving delay and wire loading) is 20 nS.
MIN.
3 TCP-Δ
1 TCP-Δ
1 TCP-Δ
6 TCP-Δ
TYP.
-
-
-
6 TCP
MAX.
3 TCP+Δ
-
-
-
UNIT
nS
nS
nS
nS
7.3.5 Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
TPDH
TPDA
MIN.
1 TCP
0
1 TCP
TYP.
-
-
-
MAX.
-
-
-
UNIT
nS
nS
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
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Publication Release Date: December 4, 2006
Revision A11