W83195BR-341 Datasheet, PDF(2/26 Page) Winbond – WINBOND CLOCK GENERATOR FOR VIA P4/KT SERIES CHIPSET

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W83195BR-341 Datasheet, PDF (2/26 Pages) Winbond – WINBOND CLOCK GENERATOR FOR VIA P4/KT SERIES CHIPSET

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W83195BR-341

Table of Contents-

1. GENERAL DESCRIPTION ..........................................................................................................1

2. FEATURES ..................................................................................................................................1

3. PIN CONFIGURATION ................................................................................................................2

4. BLOCK DIAGRAM .......................................................................................................................3

5. PIN DESCRIPTION......................................................................................................................3

5.1 Crystal I/O ........................................................................................................................................ 4

5.2 CPU, AGP, PCI Clock Outputs ....................................................................................................... 4

5.3 Fixed Frequency Outputs................................................................................................................ 5

5.4 DRAM Buffer.................................................................................................................................... 5

5.5 I2C Control Interface ....................................................................................................................... 5

5.6 Output Control Pins ......................................................................................................................... 6

5.7 Power an GND Pins ........................................................................................................................ 6

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE .................................................7

I2C CONTROL AND STATUS REGISTERS ................................................................................8

7.1 Register 0: Frequency Select (Default = 08h) ................................................................................ 8

7.2 Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default: A1h).......................................... 8

7.3 Register 2: PCI Clock (1 = Enable, 0 = Disable) (Default: FEh) .................................................... 9

7.4 Register 3: REF, 24_48,48,AGP Clock (1 = Enable, 0 = Disable) (Default: F7h)......................... 9

7.5 Register 4,5 Reserved..................................................................................................................... 9

7.6 Register 6: M/N Program (Default: 8Bh).........................................................................................9

7.7 Register 7: M/N Program (Default: 2Fh).......................................................................................10

7.8 Register 8: Spread Spectrum Program (Default: 1Fh).................................................................10

7.9 Register 9: Divider Ratio (Default: 03h) ........................................................................................10

7.10 Register 10: Control (Default: 0Ah)........................................................................................11

7.11 Register 11: Control (Default: E7h)........................................................................................12

7.12 Register 12: Control (Default: 3Ch) .......................................................................................12

7.13 Register 13: Control (Default: 24h) ........................................................................................13

7.14 Register 14: Control (Default: 56h) ........................................................................................13

7.15 Register 15: Slew Rate Control (Default: 55h) ......................................................................13

7.16 Register 16: DRAM Buffer Control (1 = Enable, 0 = Disable) (Default: 7Fh).......................14

7.17 Register 17: Slew Rate Control (Default: CFh) .....................................................................14

7.18 Register 18: M/N Time & Type Control (Default: 5Bh)..........................................................14

7.19 Register 19: Reserved ...........................................................................................................15

7.20 Register 20: Winbond Chip ID â (Ready Only) (Default: 61h)..............................................15

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