W25Q16CL_13 Datasheet, PDF (2/72 Pages) Winbond – 2.5V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

W25Q16CL
Table of Contents
1. GENERAL DESCRIPTION ............................................................................................................... 5
2. FEATURES....................................................................................................................................... 5
3. PACKAGE TYPES............................................................................................................................ 6
3.1 Pin Configuration SOIC 150 / 208-mil, VSOP 150-MIL........................................................ 6
3.2 PAD Configuration WSON 6x5-mm ..................................................................................... 6
3.3 Pin Descriptions.................................................................................................................... 7
3.3.1 Chip Select (/CS)....................................................................................................................7
3.3.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .......................................7
3.3.3 Write Protect (/WP) ................................................................................................................7
3.3.4 HOLD (/HOLD) .......................................................................................................................7
3.3.5 Serial Clock (CLK)..................................................................................................................7
4. BLOCK DIAGRAM ............................................................................................................................ 8
5. FUNCTIONAL DESCRIPTION ......................................................................................................... 9
5.1 SPI OPERATIONS ............................................................................................................... 9
5.1.1 Standard SPI Instructions.......................................................................................................9
5.1.2 Dual SPI Instructions ..............................................................................................................9
5.1.3 Quad SPI Instructions ............................................................................................................9
5.1.4 Hold Function .........................................................................................................................9
5.2 WRITE PROTECTION ....................................................................................................... 10
5.2.1 Write Protect Features .........................................................................................................10
6. CONTROL AND STATUS REGISTERS ........................................................................................ 11
6.1 STATUS REGISTER .......................................................................................................... 11
6.1.1 BUSY ...................................................................................................................................11
6.1.2 Write Enable Latch (WEL) ....................................................................................................11
6.1.3 Block Protect Bits (BP2, BP1, BP0)......................................................................................11
6.1.4 Top/Bottom Block Protect (TB).............................................................................................11
6.1.5 Sector/Block Protect (SEC) ..................................................................................................11
6.1.6 Complement Protect (CMP) .................................................................................................12
6.1.7 Status Register Protect (SRP1, SRP0) ................................................................................12
6.1.8 Erase/Program Suspend Status (SUS) ................................................................................12
6.1.9 Security Register Lock Bits (LB3, LB2, LB1) ........................................................................12
6.1.10 Quad Enable (QE)..............................................................................................................13
6.1.11 Status Register Memory Protection (CMP = 0)...................................................................14
6.1.12 Status Register Memory Protection (CMP = 1)...................................................................15
6.2 INSTRUCTIONS................................................................................................................. 16
6.2.1 Manufacturer and Device Identification ................................................................................16
6.2.2 Instruction Set Table 1 (Erase, Program Instructions)⁽¹⁾ .......................................................17
6.2.3 Instruction Set Table 2 (Read Instructions) ..........................................................................18
-2-