W9864G6JH Datasheet, PDF (15/43 Pages) Winbond – 1M  4 BANKS  16 BITS SDRAM

W9864G6JH
9.5 AC Characteristics and Operating Condition
(VDD = 3.3V±0.3V for-5/-6, VDD = 2.7V-3.6V for -7/-7S on TA = 0°C~70°C, VDD = 3.3V±0.3V for -6I/-6A on TA = -40°C~85°C)
(Notes: 5, 6)
PARAMETER
-5
-6/-6I/-6A
-7/-7S
SYM.
UNIT NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
Ref/Active to Ref/Active Command
Period
t_RC 55
60
65
Active to precharge Command Period t_RAS 40 100000 42 100000 45 100000 nS
Active to Read/Write Command Delay
Time
t_RCD
15
15
20
Read/Write(a) to Read/Write(b)
Command Period
t_CCD
1
1
1
t_CK
Precharge to Active Command Period t_RP 15
15
18
Active(a) to Active(b) Command
Period
t_RRD 10
12
14
nS
CL* = 2
2
2
2
Write Recovery Time
CL* = 3
t_WR
2
2
2
t_CK
CLK Cycle Time
CL* = 2
CL* = 3
10 1000 7.5 1000 10 1000
t_CK
5
1000 6 1000 7
1000
CLK High Level Width
t_CH
2
2
2
9
CLK Low Level Width
t_CL
2
2
2
9
CL* = 2
-
6
6
10
Access Time from CLK
CL* = 3
t_AC
4.5
5
5.5
10
Output Data Hold Time
t_OH
3
3
3
Output Data High Impedance Time
t_HZ
2
5
2
6
2
7
Output Data Low Impedance Time
t_LZ
0
0
0
Power Down Mode Entry Time
t_SB
0
5
0
6
0
7
Transition Time of CLK (Rise and Fall) t_T
1
1
1
Data-in Set-up Time
t_DS 1.5
1.5
1.5
Data-in Hold Time
t_DH
1
1
1
Address Set-up Time
t_AS 1.5
1.5
1.5
Address Hold Time
t_AH
1
1
1
CKE Set-up Time
t_CKS 1.5
1.5
1.5
CKE Hold Time
t_CKH
1
1
1
Command Set-up Time
t_CMS 1.5
1.5
1.5
Command Hold Time
t_CMH
1
1
1
Refresh Time
t_REF
64
64
64
Mode register Set Cycle Time
t_RSC
2
2
2
Exit self refresh to ACTIVE command t_XSR 70
72
75
10
7
10
nS
9
9
9
9
9
9
9
9
mS
t_CK
nS
*CL = CAS Latency
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Publication Release Date: Oct. 19, 2011
Revision A03