W78LE52C Datasheet, PDF (15/23 Pages) Winbond – 8-BIT MICROCONTROLLER

W78LE52C/W78L052C
Data Read Cycle
PARAMETER
SYMBOL
MIN.
ALE Low to RD Low
TDAR
3 TCP -Δ
RD Low to Data Valid
TDDA
-
Data Hold from RD High
TDDH
0
Data Float from RD High
TDDZ
0
RD Pulse Width
TDRD
6 TCP -Δ
Notes:
1. Data memory access time is 8 TCP.
2. "Δ" (due to buffer driving delay and wire loading) is 20 nS.
TYP.
-
-
-
-
6 TCP
MAX.
3 TCP +Δ
4 TCP
2 TCP
2 TCP
-
UNIT
nS
nS
nS
nS
nS
NOTES
1, 2
1
2
Data Write Cycle
PARAMETER
SYMBOL
ALE Low to WR Low
TDAW
Data Valid to WR Low
TDAD
Data Hold from WR High
TDWD
WR Pulse Width
TDWR
Note: "Δ" (due to buffer driving delay and wire loading) is 20 nS.
MIN.
3 TCP -Δ
1 TCP -Δ
1 TCP -Δ
6 TCP -Δ
TYP.
-
-
-
6 TCP
MAX.
3 TCP +Δ
-
-
-
UNIT
nS
nS
nS
nS
Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
TPDH
TPDA
MIN.
1 TCP
0
1 TCP
TYP.
-
-
-
MAX.
-
-
-
UNIT
nS
nS
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
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Publication Release Date: April 17, 2007
Revision A4