W78E54C Datasheet, PDF (15/24 Pages) Winbond – 8-BIT MICROCONTROLLER

W78E54C/W78E054C
7.3 A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.6micron CMOS process when using 2 and 4 mA output buffers.
7.3.1 Clock Input Waveform
XTAL1
T_CH
T_CL
F OP, TCP
PARAMETER
SYMBOL
MIN.
TYP.
Operating Speed
FOP
0
-
Clock Period
TCP
25
-
Clock High
TCH
10
-
Clock Low
TCL
10
-
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
MAX.
40
-
-
-
7.3.2 Program Fetch Cycle
PARAMETER
Address Valid to ALE Low
Address Hold from ALE Low
ALE Low to PSEN Low
SYMBOL
TAAS
TAAH
TAPL
MIN.
1 TCP -Δ
1 TCP -Δ
1 TCP -Δ
TYP.
-
-
-
MAX.
-
-
-
PSEN Low to Data Valid
Data Hold after PSEN High
Data Float after PSEN High
ALE Pulse Width
PSEN Pulse Width
TPDA
TPDH
TPDZ
TALW
TPSW
-
0
0
2 TCP -Δ
3 TCP -Δ
-
-
-
2 TCP
3 TCP
2 TCP
1 TCP
1 TCP
-
-
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "Δ" (due to buffer driving delay and wire loading) is 20 nS.
UNIT
MHz
nS
nS
nS
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
NOTES
1
2
3
3
NOTES
4
1, 4
4
2
3
4
4
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Publication Release Date: October 3, 2006
Revision A4