W78C58 Datasheet, PDF (15/22 Pages) Winbond – 8-BIT MICROCONTROLLER

W78C58
Notes:
1. P00-P07, P20-P27 remain stable through entire memory cycle.
2. Memory access time is 3 Tcp.
3. Data has been latched internally prior to /PSEN going high.
4. ∆ is 20 ns (due to buffer driving delay and wire loading).
Data Read Cycle
External Data Memory Read Cycle (see Figure 7)
PARAMETER
SYMBOL MIN.
ALE Low to RD Low
TDAR
3 Tcp-∆
RD Low to Data Valid
TDDA
-
Data Hold After RD High
TDDH
0
Data Float After RD High
TDDZ
0
RD Pulse Width
TDRD
6 Tcp-∆
Notes:
1. Data Memory access time is 5 Tcp.
2. ∆ is 20 ns (due to buffer driving delay and wire loading.
TYP.
3 Tcp
-
-
-
6 Tcp
MAX.
3 Tcp+∆
4 Tcp
2 Tcp
2 Tcp
6 Tcp+∆
UINT
nS
nS
nS
nS
nS
NOTES
1, 2
1
2
Data Write Cycle
External Data Memory Write Cycle (see Figure 8)
PARAMETER
SYMBOL MIN.
ALE Low to WR Low
TDAW
3 Tcp-∆
Data Valid to WR Low
TDAD
1 Tcp-∆
Data Hold After WR High
TDWD
1 Tcp-∆
WR Pulse Width
TDWR
6 Tcp-∆
*Note: ∆ is 20 ns (due to buffer driving delay and wire loading)
TYP.
3 Tcp
-
-
6 Tcp
MAX.
3 Tcp+∆
-
-
6 Tcp+∆
UINT
nS
nS
nS
nS
NOTE
*
*
Port Access Cycle
Port Access Cycle (see Figure 9)
PARAMETER
Port Input Setup to ALE Low
Port Input Hold After ALE Low
Port Output to ALE High
SYMBOL
TPDS
TPDH
TPDA
MIN.
1Tcp
0
1Tcp-∆
TYP.
-
-
-
MAX.
-
-
-
UINT
nS
nS
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
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Publication Release Date: December 1997
Revision A5