W78L801 Datasheet, PDF (14/20 Pages) Winbond – 8-BIT MICROCONTROLLER

W78L801
Program Fetch Cycle
PARAMETER
Address Valid to ALE Low
Address Hold from ALE Low
ALE Low to PSEN Low
PSEN Low to Data Valid
Data Hold after PSEN High
Data Float after PSEN High
ALE Pulse Width
PSEN Pulse Width
SYMBOL
TAAS
TAAH
TAPL
TPDA
TPDH
TPDZ
TALW
TPSW
MIN.
1 TCP -∆
1 TCP -∆
1 TCP -∆
-
0
0
2 TCP -∆
3 TCP -∆
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "∆" (due to buffer driving delay and wire loading) is 20 nS.
TYP.
-
-
-
-
-
-
2 TCP
3 TCP
MAX.
-
-
-
2 TCP
1 TCP
1 TCP
-
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
NOTES
4
1, 4
4
2
3
4
4
Data Read Cycle
PARAMETER
SYMBOL MIN. TYP.
MAX.
ALE Low to RD Low
RD Low to Data Valid
Data Hold from RD High
Data Float from RD High
RD Pulse Width
TDAR
TDDA
TDDH
TDDZ
TDRD
Notes:
1. Data memory access time is 8 TCP.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
3 TCP -∆
-
0
0
6 TCP -∆
-
-
-
-
6 TCP
3 TCP +∆
4 TCP
2 TCP
2 TCP
-
UNIT
nS
nS
nS
nS
nS
NOTE
S
1, 2
1
2
Data Write Cycle
PARAMETER
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
SYMBOL
TDAW
TDAD
TDWD
TDWR
MIN.
3 TCP -∆
1 TCP -∆
1 TCP -∆
6 TCP -∆
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
TYP.
-
-
-
6 TCP
MAX.
3 TCP +∆
-
-
-
UNIT
nS
nS
nS
nS
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