AN-CC1002 Datasheet, PDF (1/3 Pages) Winbond – Design Considerations for ISD1700 Family

Design Considerations for ISD1700 Family
AN-CC1002
1. Introduction
Winbond’s ISD1700 family is another ChipCorder^ product, which has a Class D PWM
speaker output with wide operating voltage, ranging from 2.4V to 5.5V. This PWM
speaker driver maximizes audio volume and power efficiency. However, without
adequate system power supply and distribution design, can result in higher noise levels
than a typical speaker driver. Also, as usual, higher operating voltage induces more
power noise on the system. As a result, it increases the challenges on optimizing the
voice quality on an end-product.
This Application Note discusses the crucial factors for considerations while implementing
ISD1700 Series. Then, proposes some simple and cost-effective recommendations.
2. Decoupling Capacitors
In addition to the typical 0.1µF capacitor on the power lines, when a 10µF Aluminum
Electrolytic capacitor is added to each V_CCA, V_CCD and V_CCP power line with respect to the
related ground path, it can reduce the noise from the power supplies. The locations of
these capacitors should be as close to the device as possible. By doing so, it enhances
the voice quality. Sometimes, a 4.7µF Aluminum Electrolytic capacitor may be sufficient
for certain applications. Furthermore, we have experienced that the SMT capacitor
reduces the noise, but the result may not be as good as that using the Aluminum
Electrolytic type.
3. Layout Techniques
A good practice is to separate each power line (V_CCA, V_CCD & V_CCP) and each ground path
(V_SSA, V_SSD, V_{SSP1 &} V_SSP2) individually from the device to the system. Meanwhile, the
ISD1700 device has isolated V_CCP, V_SSP1 & V_SSP2 pads for PWM speaker driver. To
minimize the noise from the PWM speaker driver, it is vital to route an independent trace
from each related pin to the supply and ground terminals directly. The following aspects
should be taken into accounts:
• Place V_SSA and V_SSD planes/paths on one side of PCB and the V_SSP1 & V_SSP2
planes/paths on the opposite side of PCB.
• Make each V_SSA and V_SSD as one big ground plane and as large as possible. Size
the V_SSA and V_SSD planes in approximate equivalent area.
• Layout the V_SSP1 & V_SSP2 traces as large as possible and connect them to the
system ground in the shortest distance.
• Funnel each ground path back to ground terminal for better grounding effect.
• Similarly, apply independent path technique on V_CCA, V_CCD and V_CCP signals.
• The decoupling capacitors should be as close to the device as possible.
January, 2006
Page 1 / 3