W332M72V-XBX Datasheet, PDF (9/15 Pages) White Electronic Designs Corporation – 32Mx72 Synchronous DRAM

White Electronic Designs
W332M72V-XBX
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock
is defined as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back
HIGH. Once CKE is HIGH, the SDRAM must have NOP
commands issued (a minimum of two clocks) for tXSR,
because time is required for the completion of any internal
refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on VCC, VCCQ Supply relative to Vss
Voltage on NC or I/O pins relative to Vss
Operating Temperature TA (Mil)
Operating Temperature TA (Ind)
Storage Temperature, Plastic
Unit
-1 to 4.6
V
-1 to 4.6
V
-55 to +125
°C
-40 to +85
°C
-55 to +125
°C
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (NOTE 2)
Parameter
Input Capacitance: CLK
Addresses, BA0-1 Input Capacitance
Input Capacitance: All other input-only pins
Input/Output Capacitance: I/Os
Symbol
Max
Unit
CI1
9
pF
CA
34
pF
CI2
12
pF
CIO
12
pF
BGA THERMAL RESISTANCE
Description
Symbol
Max
Unit
Junction to Ambient (No Airflow)
Theta JA
13.9
C/W
Junction to Ball
Theta JB
10.3
C/W
Junction to Case (Top)
Theta JC
4.6
C/W
NOTE: Refer to Application Note “PBGA Thermal Resistance Correlation” at www.wedc.com in the application notes section for modeling conditions.
Notes
1
1
1
March 2006
Rev. 3
9
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