W3EG72126S-D3 Datasheet, PDF (8/15 Pages) White Electronic Designs Corporation – 1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL

White Electronic Designs
W3EG72126S-D3
-JD3
-AJD3
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V
AC Characteristics
335
262
263/265
202
Parameter
Symbol Min
Access window of DQs from CK, CK#
tAC -0.7
CK high-level width
tCH 0.45
CK low-level width
tCL 0.45
Clock cycle time
CL=2.5 tCK (2.5) 6
CL=2 tCK (2)
DQ and DM input hold time relative to DQS
tDH 0.45
DQ and DM input setup time relative to DQS
tDS 0.45
DQ and DM input pulse width (for each input)
tDIPW 1.75
Access window of DQS from CK, CK#
tDQSCK -0.6
DQS input high pulse width
tDQSH 0.35
DQS input low pulse width
tDQSL 0.35
DQS-DQ skew, DQS to last DQ valid, per group,
tDQSQ
per access
Write command to first DQS latching transition
tDQSS 0.75
DQS falling edge to CK rising - setup time
tDSS 0.2
DQS falling edge from CK rising - hold time
tDSH 0.2
Half clock period
tHP
tCH,
tCL
Data-out high-impedance window from CK, CK#
tHZ
Data-out low-impedance window from CK, CK#
tLZ -0.7
Address and control input hold time (fast slew rate)
tIHf 0.75
Address and control input set-up time (fast slew rate)
tISf 0.75
Address and control input hold time (slow slew rate)
tIHs
0.8
Address and control input setup time (slow slew rate)
tISs
0.8
Address and control input pulse width (for each input) tIPW 2.2
LOAD MODE REGISTER command cycle time
tMRD
12
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tQH
tHP-
tQHS
Data hold skew factor
tQHS
ACTIVE to PRECHARGE command
tRAS
42
ACTIVE to READ with Auto precharge command
tRAP
15
ACTIVE to ACTIVE/AUTO REFRESH command period tRC 60
AUTO REFRESH command period
tRFC
72
Max Min Max Min Max Min Max Units Notes
+0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns
0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 16
0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 16
13 7.5 13 7.5 13 7.5 13 ns 22
7.5 13 7.5 13 7.5 13 ns 22
0.5
0.5
0.5
ns 14,17
0.5
0.5
0.5
ns 14,17
1.75
1.75
1.75
ns 17
+0.6 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns
0.35
0.35
0.35
tCK
0.35
0.35
0.35
tCK
0.45
0.5
0.5
0.5 ns 13,14
1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
0.2
0.2
0.2
tCK
0.2
0.2
0.2
tCK
tCH,
tCH,
tCH,
ns
tCL
tCL
tCL
+0.7
+0.75
+0.75
+0.75 ns
-0.75
-0.75
-0.75
ns
0.90
0.90
0.90
ns
0.90
0.90
0.90
ns
1
1
1
ns
1
1
1
ns
2.2
2.2
2.2
ns
15
15
15
ns
tHP-
tHP-
tHP-
ns
tQHS
tQHS
tQHS
0.55
0.75
0.75
0.75 ns
70,000 40 120,000 40 120,000 40 120,000 ns
15
15
15
ns
60
60
60
ns
75
75
75
ns
18
8,19
8,20
6
6
6
6
13,14
15
21
November 2004
Rev. 3
8
White Electronic Designs Corporation • [phone] • www.wedc.com