WV3HG264M72EER-D7 Datasheet, PDF (6/11 Pages) White Electronic Designs Corporation – 1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM

White Electronic Designs ^{WV3HG264M72EER-D7}
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only; TA = 0°C, VCC = 1.9V
Symbol Parameter Condition
806 665 534 403 Unit
Operating
ICC0*
one bank
active-
tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
1337 1292 1292
mA
precharge;
Operating
one bank IOUT = 0mA; BL = 4; CL = CL(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is
ICC1* active-
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
TBD 1472 1427 1427 mA
read-
Data bus inputs are SWITCHING; Data pattern is same as ICC4W.
precharge;
ICC2P**
Precharge
power-
down
current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
TBD 644 644 644 mA
Precharge
ICC2Q**
quite
standby
All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
TBD
1130 1040 1040
mA
current;
ICC2N**
Precharge
standby
current;
All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus
inputs are STABLE; Data bus inputs are SWITCHING
TBD
1220 1130 1130
mA
ICC3P**
Active
power-
down
current;
All banks open; tCK = tCK(ICC), CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs are
FLOATING
Fast PDN Exit
MRS(12) = 0
Slow PDN Exit
MRS(12) = 1
TBD 1040 1040 1040 mA
TBD 716 716 716 mA
ICC3N**
Active
standby
current;
All banks open; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS#
is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
TBD 1490 1400 1400 mA
Operating All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(ICC);
ICC4W* burst write tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; TBD 1832 1652 1562 mA
current; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
ICC4R*
Operating
burst read
current;
All banks open; Continuous burst reads; TOUT = 0mA; BL = 4; CL = CL(ICC); AL = 0;
tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W.
TBD 1877 1697 1562 mA
Burst auto tCK = tCK(ICC); Refresh command at every tRC(ICC) interval; CKE is HIGH; CS# is HIGH
ICC5** refresh between valid commands; Other control and address bus inputs are SWITCHING;
current; Data bus inputs are SWITCHING
TBD 3200 3020 3020 mA
Self
ICC6** refresh
current;
CK and CK# at 0V; CKE < 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Normal
TBD 144 144 144 mA
ICC7*
Operating
bank
interleave
read
current;
All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(ICC); AL = tRCD(ICC) - 1*tCK(ICC);
tCK = tCK(ICC); tRC = tRC(ICC); tRRD = tRRD MIN(ICC) = 1*tCK(ICC); CKE is HIGH; CS# is HIGH
between valid commands; Address bus inputs are STABLE during DESELECTs; Data
bus inputs are SWITCHING
TBD
2552 2552 2552
mA
Notes:
ICC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
August 2006
Rev. 3
6
White Electronic Designs Corporation • [phone] • www.wedc.com