WV3HG264M64EEU-D4 Datasheet, PDF (6/11 Pages) White Electronic Designs Corporation – 1GB - 2x64Mx64 DDR2 SDRAM UNBUFFERED

White Electronic Designs ^{WV3HG264M64EEU-D4}
ADVANCED
ICC SPECIFICATION
Symbol Proposed Conditions
806 665 534 403 Units
ICC0* Operating one bank active-precharge;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD 744 704 704 mA
ICC1* Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
TBD
864
824
824
mA
same as ICC4W
ICC2P**
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
TBD 128 128 128 mA
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
TBD 560 480 480 mA
ICC2N**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
TBD 640 560 560 mA
ICC3P**
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
TBD 480 480 480 mA
TBD 192 192 192 mA
ICC3N** Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
TBD
880
800
800
mA
SWITCHING
ICC4W*
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
TBD 1184 1024 944 mA
ICC4R* Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
TBD
1224 1064
944
mA
inputs are SWITCHING; Data pattern is same as ICC4W
ICC5** Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
TBD 2400 2240 2240 mA
Self refresh current;
ICC6** CK and CK# at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Normal
TBD 128 128 128 mA
ICC7* Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK =
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
TBD 1824 1824 1824 mA
commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Note:
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
February 2006
Rev. 2
6
White Electronic Designs Corporation • [phone] • www.wedc.com