W3EG72255S-D3 Datasheet, PDF (6/15 Pages) White Electronic Designs Corporation – 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL

White Electronic Designs
W3EG72255S-D3
-JD3
-AJD3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes PLL and register power
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby Current
Idle Standby Current
Active Power-Down Standby
Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
Rank 1
Conditions
One device bank; Active - Precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
One device bank; Active-Read-
Precharge Burst = 2; tRC = tRC (MIN);
tCK = tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
All device banks idle; Power-down mode;
tCK = tCK (MIN); CKE = (low)
CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
One device bank active; Power-Down
mode; tCK (MIN); CKE = (low)
CS# = High; CKE = High; One device
bank; Active-Precharge;tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address
and other control inputs changing once
per clock cycle.
Burst = 2; Reads; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle; tCK
= tCK (MIN); lOUT = 0mA.
Burst = 2; Writes; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
tRC = tRC (MIN)
CKE ≤ 0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK(MIN); Address and control inputs
change only during Active Read or Write
commands.
DDR333@CL=2.5
Max
4725
5265
180
1930
1260
2110
5355
5535
7640
455
9675
DDR266:@CL=2, 2.5
Max
4725
5265
180
1930
1260
2110
5355
5175
7640
455
9585
DDR200@CL=2
Max
4725
5265
180
1930
1260
2110
5355
5175
7640
455
9585
Units
mA
Rank 2
Standby
State
IDD3N
mA
IDD3N
rnA
IDD2P
mA
IDD2F
mA
IDD3P
mA
IDD3N
mA
IDD3N
rnA
IDD3N
mA
IDD3N
mA
IDD6
mA
IDD3N
November 2004
Rev. 2
6
White Electronic Designs Corporation • [phone] • www.wedc.com